Link Up issue of E810 with FPGA

[LChen23]

1. E810 could link up with intel Stratix 10 FPGA H-tile 100G MAC+PHY with RSFEC 528,514 but  failed to link up with 100G without RS-FEC, Please confirm if the RSFEC is MUST for 100G?

[Fikri_Intel]

Hi LChen23,

Thank you for contacting Intel.

We appreciate you reaching out to us regarding the reported issue. We would like to provide further clarification regarding the FEC (Forward Error Correction) configuration for the Intel® Ethernet Controller E810.

As outlined in the Intel® Ethernet Controller E810 Specification Update, a successful link requires both endpoints to be configured with the exact same FEC encoding and lane alignment marker spacing. Mismatched configurations can lead to connectivity issues or degraded performance.

For reference, please review the following documents:

https://www.intel.com/content/www/us/en/secure/design/internal/content-details.html?DocID=616943

https://www.intel.com/content/www/us/en/secure/design/internal/content-details.html?DocID=613875

We recommend verifying the settings on both ends to ensure compatibility.

Regards,

Fikri O.