Need Guidance 10G Ethernet System

[Altera_Forum]

Hello everyone. 

 I have a problem on which i have to send words of 64-bits between two FPGAs. Those words are sent as Avalon MM request/responses. My supervisor bought the "DUAL XAUI TO SFP+" daughter cards in order to connect two Altera Stratix V Dev. Kits, for example.  I am a little bit lost on how to start, but I had some ideas and I would like to share with you to see if they're right.  I've found a project on altera's installation folder named altera_eth_10g_mac_xaui, on which i found that this instantiates a "Altera Ethernet 10G Design Example" on Qsys and make some interconnections. I have realized that on top.v file, there is a loopback between avalon-ST tx and rx FIFOs. If I substitute this loopback with my own module (including necessary adapters from Avalon-MM to Avalon-ST), I would be able to transmit those words between two FPGAs?  Please give me a hand guys, thank you very much.

[Altera_Forum]

Yes, should be fine.

[Altera_Forum]

Thank you Socrates. 

 I've removed the address swap loopback and inserted one Test Pattern Generator and one Test Pattern Checker. I've connected both to a NIOS Processor and tried running. Qsys alerted me that rx_sc_fifo_out and the in port from the Test Checker must be on the same clock domain. I guessed that this clock would be then xgmii_rx_clk. The problem is that I can't even reset the Checker on NIOS, the process simply hangs.  Any help is highly appreciated!

[Altera_Forum]

Solved (I think) by using a DC FIFO.

[Altera_Forum]

Hello once again. I've managed to connect the Avalon-ST interfaces to a NIOS II processor by using DC FIFOs. The problem is that when I try to read/write the internal registers from the Design Example, my NIOS simply hangs. I've noticed also that running the original project and trying to use the available TCL script to configure and run the system, it also hangs when trying to write the MAC address inside the MAC Registers. Does anyone knows why this happens? Thank you once again.

[Altera_Forum]

Just to give more information, I was running the tutorial showed on "10-Gbps Ethernet Mac MegaCore Function User Guide" at page 36. When I run the step 4 on section 3.7.1 (source config.tcl) the TCL hangs when writing the MAC Address to the system.

[Altera_Forum]

Try checking the Avalon signals around the MAC. The hang could come from the fact that the MAC keeps the waitrequest signal high. This can happen for example if the MAC is missing one of its clocks.

[Altera_Forum]

Thanks for the reply. 

 On the original project (and on mine as well) the clocks are connected as: -mm_clk <- clk_50MHz (50 MHz) -ref_clk <- ref_clk (156.25 MHz) -tx_clk <- xgmii_rx_clk (156.25 MHz)  so I think that there isn't any missing clocks to pin... It only sounded strange to me connect the xgmii_rx_clk output directly to tx_clk. But on page 148 from the User Guide this is shown as valid...    --- Quote Start ---  Try checking the Avalon signals around the MAC. The hang could come from the fact that the MAC keeps the waitrequest signal high. This can happen for example if the MAC is missing one of its clocks.  --- Quote End ---  

[Altera_Forum]

Can you check those signals (clocks, wait_request, and all the Avalon Memory Mapped signals) with SignalTap and see if the TSE is receiving and processing correctly the register write requests?

[Altera_Forum]

Thanks, I'll do that. 

 In the meantime, i wrote on the loopback registers by using those two functions:  IOWR_32DIRECT(MERLIN_MASTER_TRANSLATOR_0_BASE, 0x10200 + 0x0, 0); IOWR_32DIRECT(MERLIN_MASTER_TRANSLATOR_0_BASE, 0x10200 + 0x8, 1);  where 0x10200 is the base address for the Loopback module.  and the system didn't halt. But when I try to read those registers, then everything hangs.  Thank you for the help!    --- Quote Start ---  Can you check those signals (clocks, wait_request, and all the Avalon Memory Mapped signals) with SignalTap and see if the TSE is receiving and processing correctly the register write requests?  --- Quote End ---  

[Altera_Forum]

There you go, the signalTap for those three operations:  

 /* Disable Line LoopBack */ IOWR_32DIRECT(MERLIN_MASTER_TRANSLATOR_0_BASE, 0x10200 + 0x0, 0); /* Enable Local LoopBack */ IOWR_32DIRECT(MERLIN_MASTER_TRANSLATOR_0_BASE, 0x10200 + 0x8, 1); /* Check RX_CRCCHECK_CONTROL REGISTER */ printf("RX_CRCCHECK_CONTROL: %d\n", IORD_32DIRECT(MERLIN_MASTER_TRANSLATOR_0_BASE, 0x0 + 0x80));  When the read is requested, the waitrequest hangs forever... Also, this is not a TSE module, this is the 10gbE Design Example module on Qsys.  The SignalTap results are attached. https://www.alteraforum.com/forum/attachment.php?attachmentid=7200   Thank you!    --- Quote Start ---  Can you check those signals (clocks, wait_request, and all the Avalon Memory Mapped signals) with SignalTap and see if the TSE is receiving and processing correctly the register write requests?  --- Quote End ---  

[Altera_Forum]

Hello again. 

 I've decided to create the project from scratch (Instantiate separatedly the MAC and XAUI interfaces) and pin it by myself. For now I've created a system with a NIOS and the 10gb Ethernet MAC Module, and I can read successfully the registers from the module. I will test the module by loopbacking it, and then include the XAUI module.  Anyway, thanks everyone for the help!

[Altera_Forum]

Hello once more. 

 After R/W on registers from MAC was successful, I've connected the XAUI PHY to the MAC. I've instantiated it as a megafunction, and then imported to Qsys as shown on the attached figure. I've connected the NIOS to both XAUI PHY and MAC control ports, and I can change XAUI registers, but if I try to read anything from the MAC, the NIOS hangs. Without the XAUI, the MAC works fine.  https://www.alteraforum.com/forum/attachment.php?attachmentid=7203   I've connected the pll_ref_clk to the ref_clk pins (AA2 and AA1) as used on design example. Doest anyone knows what can be wrong?  Thanks.

[Altera_Forum]

Sorry I missed the 10Ge part and thought you were using a TSE core. Unfortunately I don't have experience with the 10G core. Could there be any clock related problem coming from one of the XAUI signals?

[Altera_Forum]

Yes. I've realized that xgmii_rx_clk output from XAUI Phy is not working. But I still don't have a clue why it isn't working... 

   --- Quote Start ---  Sorry I missed the 10Ge part and thought you were using a TSE core. Unfortunately I don't have experience with the 10G core. Could there be any clock related problem coming from one of the XAUI signals?  --- Quote End ---  

[Altera_Forum]

Hello again. 

 I have tried to run even the original Altera projects (i.e. an638) and had no success. As always, xgmii_rx_clk didn't work, which made me think that could perhaps be some type of hardware fault.  So I've switched my project to a Stratix V and it worked fine with the loopback!  So again, thanks for everyone who help me!

[Altera_Forum]

Hey comododragon, I'm trying to use the 10G ethernet system for Stratix V. I want to connect 

the FPGA to a Ethernet dual port connected to my desktop via an SFP+ copper cable. Can you give me some advice on what to do, I've been having troubles with the code. The Ethernet dual port doesn't recognize the FPGA device after compiling the code. Thanks!

[Altera_Forum]

--- Quote Start ---  Hey comododragon, I'm trying to use the 10G ethernet system for Stratix V. I want to connect the FPGA to a Ethernet dual port connected to my desktop via an SFP+ copper cable. Can you give me some advice on what to do, I've been having troubles with the code. The Ethernet dual port doesn't recognize the FPGA device after compiling the code. Thanks!  --- Quote End ---    Any luck with this?  I'm about to embark on the same thing but not entirely sure what the best approach is.