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Altera_Forum
Honored Contributor I
1,249 Views

Problems in getting the Triple Speed Ethernet core to work

Hello everyone, 

 

I am using a Cyclone V on a sockit board (link here) (https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=816) (provided by Terasic), connecting an hsmc-net daughter card (link here) (https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=355) to it in order to create a system that can communicate using Ethernet while communication that is both transmitted and received goes through the FPGA - The problem is, I am having a really, really hard time getting this system to work using Altera's Triple Speed Ethernet core. 

 

I am using Qsys to construct the system that contains the Triple Speed Ethernet core, instantiating it inside a VHDL wrapper that also contains an instantiation of a packet generator module, connected directly to the transmit Avalon-ST sink port of the TSE core and controlled through an Avalon-MM slave interface connected to a JTAG to Avalon Master bridge core which has it's master port exported to the VHDL wrapper as well. 

 

Then, using System Console, I am configuring the Triple Speed Ethernet core as described in the core's user guide (link here) (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ethernet.pdf) at section 5-26 (Register Initialization) and instruct the packet generator module (also using System Console) to start and generate Ethernet packets into the TSE core's transmit Avalon-ST sink interface ports. 

 

Although having everything configured exactly as described in the core's user guide (linked above) I cannot get it to output anything on the MII/GMII output interfaces, neither get any of the statistics counters to increase or even change - clearly, I am doing something wrong, or missing something, but I just can't find out what exactly it is. 

 

Can any one please, please help me with this? :( 

Thanks ahead, 

Itamar
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3 Replies
Altera_Forum
Honored Contributor I
42 Views

Well, it looks like it could be either hardware (Quartus design, connection, etc) or software issue. Unfortunately I couldn't find any examples with TSE IP+Terasic card. 

 

One thing I would suggest checking is the constraint setting (in the sdc file), since the FPGA is connecting to an external PHY. Perhaps the constraint file in the Terasic example (downloaded from https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=71&no=355&partno=3&ti...) and the example here: https://rocketboards.org/foswiki/view/projects/cyclonevrgmiiexampledesign can help you.
Altera_Forum
Honored Contributor I
42 Views

 

--- Quote Start ---  

Well, it looks like it could be either hardware (Quartus design, connection, etc) or software issue. Unfortunately I couldn't find any examples with TSE IP+Terasic card. 

 

One thing I would suggest checking is the constraint setting (in the sdc file), since the FPGA is connecting to an external PHY. Perhaps the constraint file in the Terasic example (downloaded from https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=71&no=355&partno=3&ti...) and the example here: https://rocketboards.org/foswiki/view/projects/cyclonevrgmiiexampledesign can help you. 

--- Quote End ---  

 

 

I have requested an example using the TSE IP core on the Terasic card from Terasic, you can find it here (http://mail.terasic.com.cn/~wyzhou/sockit_net.zip), but I sill could not manage to make the thing work - even using Terasic's example desugb!
Altera_Forum
Honored Contributor I
42 Views

Did you try a layered approach? (put PHY in loopback mode, then put MAC in loopback mode, then put software in loopback mode). 

 

If PHY loopback does not work, you know it's the PHY layer that needs to be addressed. One thing that hung me up is that you must match the PHY MDIO timing settings to your physical layer. If you are connecting to a switch or NIC, you will have to set the PHY to the correct speed and autonegotiation. It's not enough to just configure the TSE Megacore you have to also configure and initialize the PHY chip. 

 

Of course, before that, I would check to make sure your Ethernet cables are made correctly with a cable checker.