TSE Ethernet RGMII for NiosII running Linux

[Altera_Forum]

I have been trying to get a SoC that would run Linux for the NiosII. Then I want it to support Ethernet. I have been using TSE so far, but no success.  

 Does anyone has some ideas about how I could have a starting point? I would like to have a functional system that would run Linux on NiosII and support TSE with RGMII. I have tried so many permutations on the design, but I have not succeeded so far.

[Altera_Forum]

this is part of my code: 

 /======================================================= // This code is generated by Terasic System Builder //=======================================================  module de2_115_dtlinux_ethernet(   //////////// CLOCK //////////  CLOCK_50,  CLOCK2_50,  CLOCK3_50,   //////////// Ethernet 0 //////////  ENET0_GTX_CLK,  ENET0_INT_N,  ENET0_LINK100,  ENET0_MDC,  ENET0_MDIO,  ENET0_RST_N,  ENET0_RX_CLK,  ENET0_RX_COL,  ENET0_RX_CRS,  ENET0_RX_DATA,  ENET0_RX_DV,  ENET0_RX_ER,  ENET0_TX_CLK,  ENET0_TX_DATA,  ENET0_TX_EN,  ENET0_TX_ER,  ENETCLK_25,   //////////// SDRAM //////////  DRAM_ADDR,  DRAM_BA,  DRAM_CAS_N,  DRAM_CKE,  DRAM_CLK,  DRAM_CS_N,  DRAM_DQ,  DRAM_DQM,  DRAM_RAS_N,  DRAM_WE_N  );  //======================================================= // PARAMETER declarations //=======================================================   //======================================================= // PORT declarations //=======================================================  //////////// CLOCK ////////// input CLOCK_50; input CLOCK2_50; input CLOCK3_50;  //////////// Ethernet 0 ////////// output ENET0_GTX_CLK; input ENET0_INT_N; input ENET0_LINK100; output ENET0_MDC; inout ENET0_MDIO; output ENET0_RST_N; input ENET0_RX_CLK; input ENET0_RX_COL; input ENET0_RX_CRS; input [3:0] ENET0_RX_DATA; input ENET0_RX_DV; input ENET0_RX_ER; input ENET0_TX_CLK; output [3:0] ENET0_TX_DATA; output ENET0_TX_EN; output ENET0_TX_ER; input ENETCLK_25;  //////////// SDRAM ////////// output [12:0] DRAM_ADDR; output [1:0] DRAM_BA; output DRAM_CAS_N; output DRAM_CKE; output DRAM_CLK; output DRAM_CS_N; inout [31:0] DRAM_DQ; output [3:0] DRAM_DQM; output DRAM_RAS_N; output DRAM_WE_N;   //======================================================= // REG/WIRE declarations //======================================================= wire eth_mode, ena_10; wire core_reset_n; wire sys_clk, clk_125, clk_25, clk_2p5, tx_clk; wire mdc, mdio_in, mdio_oen, mdio_out;   //======================================================= // Structural coding //======================================================= assign ENET0_RESET_N = core_reset_n;  assign mdio_in = ENET0_MDIO; assign ENET0_MDC = mdc; assign ENET0_MDIO = mdio_oen ? 1'bz : mdio_out;  assign tx_clk = eth_mode ? clk_125 : // GbE Mode = 125MHz clock  ena_10 ? clk_2p5 : // 10Mb Mode = 2.5MHz clock  clk_25; // 100Mb Mode = 25 MHz clock  tse_pll tse_pll_inst (  //.areset(areset_sig) , // input areset_sig  .inclk0(CLOCK_50) , // input inclk0_sig  .c0(sys_clk) , // output c0_sig  .c1(clk_125) , // output c1_sig  .c2(clk_25) , // output c2_sig  .c3(clk_2p5) , // output c3_sig  .locked(core_reset_n) // output locked_sig );     tse_ddio tse_ddio_inst (  .datain_h(1'b1) , // input [0:0] datain_h_sig  .datain_l(1'b0) , // input [0:0] datain_l_sig  .outclock(tx_clk) , // input outclock_sig  .dataout(ENET0_GTX_CLK) // output [0:0] dataout_sig );    SoC4DTLinux u0 (  .altpll_0_c1_sdram_clk_clk (DRAM_CLK), // altpll_0_c1_sdram_clk.clk  .clk_clk (CLOCK_50), // clk.clk  .reset_reset_n (1'b1), // reset.reset_n  .sdram_mem_controller_wire_addr (DRAM_ADDR), // sdram_mem_controller_wire.addr  .sdram_mem_controller_wire_ba (DRAM_BA), // .ba  .sdram_mem_controller_wire_cas_n (DRAM_CAS_N), // .cas_n  .sdram_mem_controller_wire_cke (DRAM_CKE), // .cke  .sdram_mem_controller_wire_cs_n (DRAM_CS_N), // .cs_n  .sdram_mem_controller_wire_dq (DRAM_DQ), // .dq  .sdram_mem_controller_wire_dqm (DRAM_DQM), // .dqm  .sdram_mem_controller_wire_ras_n (DRAM_RA_N), // .ras_n  .sdram_mem_controller_wire_we_n (DRAM_WE_N), // .we_n  .tse_pcs_mac_tx_clock_connection_clk (tx_clk), // tse_pcs_mac_tx_clock_connection.clk  .tse_pcs_mac_rx_clock_connection_clk (ENET0_RX_CLK), // tse_pcs_mac_rx_clock_connection.clk  .tse_mac_status_connection_set_10 (1'b0), // tse_mac_status_connection.set_10  .tse_mac_status_connection_set_1000 (1'b0), // .set_1000  .tse_mac_status_connection_eth_mode (eth_mode), // .eth_mode  .tse_mac_status_connection_ena_10 (ena_10), // .ena_10  .tse_mac_rgmii_connection_rgmii_in (ENET0_RX_DATA), // tse_mac_rgmii_connection.rgmii_in  .tse_mac_rgmii_connection_rgmii_out (ENET0_TX_DATA), // .rgmii_out  .tse_mac_rgmii_connection_rx_control (ENET0_RX_DV), // .rx_control  .tse_mac_rgmii_connection_tx_control (ENET0_TX_EN), // .tx_control  .tse_mac_mdio_connection_mdc (mdc), // tse_mac_mdio_connection.mdc  .tse_mac_mdio_connection_mdio_in (mdio_in), // .mdio_in  .tse_mac_mdio_connection_mdio_out (mdio_out), // .mdio_out  .tse_mac_mdio_connection_mdio_oen (mdio_oen) // .mdio_oen  );     endmodule