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Altera_Forum
Honored Contributor I
1,018 Views

Which board should I buy?

Hello everyone,  

 

So I need a device that have:  

- 2 input 

+ 1 for data (analog raw data)  

+ 1 for external clock. The data would be sampled at the clock speed to get bit 0 (low voltage) or 1 (high voltage) for now. 

- 1 output 

+ though Ethernet/USB port so that the data will be transfer to computer/laptop and be processed there. 

- The data rates would be from around 50 Mbps to higher. 

 

It seems to me like the Cyclone IV GX Transceiver can satisfy all my requirements, isn't it? 

 

Can anyone please suggest me which devices/board to buy for that purpose?  

 

I am not a hardware guy and just start learning so any advises/suggestions would be highly appreciated!  

 

Thank you.
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15 Replies
Altera_Forum
Honored Contributor I
76 Views

What is your maximum data rate?  

 

The CIV GX transceiver's minimum data rate is 600Mbps which is higher than your 50Mbps. If your max data rate is < 840Mbps, you can use LVDS instead of transceiver. I believe part without transceiver will be cheaper.
Altera_Forum
Honored Contributor I
76 Views

Thanks for replying my post! 

 

Currently my data rate is around 50 Mbps but it will be increased in the future. And I thought I can reduce the data rate of CIV GX by introducing redundant data? 

Could you tell me a little bit more detail about LVDS and suggest which one I should buy if possible? Once again, I'm not a hardware guy. 

 

 

--- Quote Start ---  

What is your maximum data rate?  

 

The CIV GX transceiver's minimum data rate is 600Mbps which is higher than your 50Mbps. If your max data rate is < 840Mbps, you can use LVDS instead of transceiver. I believe part without transceiver will be cheaper. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
76 Views

LVDS is a high speed general purpose differential IO in the CIV devices. Based on the data sheet, it can run up to 840Mbps for the fastest speed grade. You can check the CIV device handbook and look for LVDS to get further details.

Altera_Forum
Honored Contributor I
76 Views

Check out this chapter of the CIV handbook -> https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51006.... for details on LVDS.

Altera_Forum
Honored Contributor I
76 Views

 

--- Quote Start ---  

So I need a device that have:  

- 2 input 

+ 1 for data (analog raw data) 

--- Quote End ---  

You don't say anything about what this is. However, Cyclone IV is not going to accept anything analogue without an external ADC. 

 

 

--- Quote Start ---  

Ethernet/USB port so that the data will be transfer to computer 

--- Quote End ---  

Either of these solutions will require an external Phy. Again, Cyclone IV won't solve that need on it's own. 

 

So, I'm not sure what features of a GX device you'll use. All your interfaces will be handled by other devices and the FPGA (probably) won't interface to those with the transceivers a GX device offers. 

 

Cyclone IV would be a good choice of family. However, you'll have to find a development board with the other interface features you need. Have a look through the available cyclone development kits (https://www.altera.com/products/boards_and_kits/all-development-kits.html#squares-box-3). You don't need anything very expensive. However, you might not find anything with all the peripherals you need (DAC, USB/Ethernet). Perhaps look for something with Ethernet on board and solve the analogue requirement with a plug in daughter board. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
76 Views

Thanks for your repsonse!!! 

 

We try to have the input data as square wave. Right now, we have a solution using beagle-bone board where we connect the input directly to a pin, then we just have the assembly code to compare this pin to low/high (set/clear) and get the value (1 bit per sampling). But we want to increase the speed so I think FPGA might help? 

 

I try to find one thing that have it all but it doesn't seem to be possible? 

 

So your solution would be Input -> ADC -> Transceiver -> Phy -> Laptop? 

 

Could you give me a concrete solution? (sorry I'm so retarded) 

 

 

 

 

--- Quote Start ---  

You don't say anything about what this is. However, Cyclone IV is not going to accept anything analogue without an external ADC. 

 

Either of these solutions will require an external Phy. Again, Cyclone IV won't solve that need on it's own. 

 

So, I'm not sure what features of a GX device you'll use. All your interfaces will be handled by other devices and the FPGA (probably) won't interface to those with the transceivers a GX device offers. 

 

Cyclone IV would be a good choice of family. However, you'll have to find a development board with the other interface features you need. Have a look through the available cyclone development kits (https://www.altera.com/products/boards_and_kits/all-development-kits.html#squares-box-3). You don't need anything very expensive. However, you might not find anything with all the peripherals you need (DAC, USB/Ethernet). Perhaps look for something with Ethernet on board and solve the analogue requirement with a plug in daughter board. 

 

Cheers, 

Alex 

--- Quote End ---  

Altera_Forum
Honored Contributor I
76 Views

Hi, it is better to start and talk to some sales guy and in order to provide some suggestion as you also don't want to over kill your board if your implementation doesn't need that powerful product line..

Altera_Forum
Honored Contributor I
76 Views

I suggest you have a look at Terasic's de1-soc board (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=836&partno=1). This has everything on that you need: ADC and both Ethernet & USB Phys. 

 

The solution path you need is: Input -> ADC -> FPGA -> Phy -> Laptop 

 

In the interests of simplicity I suggest your interface to the laptop should be a USB UART to start with. It won't give you the 50Mbps bandwidth but it's a far easier interface to get your head round. Once you've cracked this then perhaps consider the Ethernet path. 

 

A small gotcha with the solution I'm suggesting. The FPGA features a Hard Processor System (HPS) and both Ethernet & USB Phys are connected to that and not the FPGA fabric. However, both can be connected to the FPGA fabric. So, you don't have to use the HPS. This App Note: mapping hps ip peripheral signals to the fpga interface (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an706.pdf), describes how to do this. 

 

Finally, if you do head down the Ethernet interface route, you might want to consider using the HPS. Realising this data path is far more involved and, depending on your experience/persuasion, using the HPS could make this much easier. The Ethernet Phy is attached to the HPS for good reason. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
76 Views

yes, Alex.. is correct.. de nano is more suitable for your usage.

Altera_Forum
Honored Contributor I
76 Views

SO I ended up with DE2i-150 board.  

 

Trying to connect the board with a computer using Ethernet. Altera has a tutorial ftp://ftp.altera.com/up/pub/altera_material/15.0/tutorials/de2-115/using_triple_speed_ethernet.pdf but it is for DE2-115.  

I am stuck at the "pin assignment" step, don't know how to modify it for DE2i-150. Any helps/suggestions?
Altera_Forum
Honored Contributor I
76 Views

Refer to the "DE2i_150_Golden_top" example project that comes on the CD with the board. This is an empty project (no functioning rtl) with all the FPGA's connections and pin assignments already made for you. 

 

The DE2-115 uses the same Marvel phy as the DE2i-150 and is connected in the same way. So, I'd hope the 'Triple-Speed Ethernet on DE2-115' guide should be easily applied to the DE2i-150 board. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
76 Views

the Altera made board is alot more expensive than terasic one....

Altera_Forum
Honored Contributor I
76 Views

The DE2-155 use enet0 and enet1 but I don't know how can I modify them for DE2i-150.

Altera_Forum
Honored Contributor I
76 Views

so how much you bought for this kit?

Altera_Forum
Honored Contributor I
76 Views

So, the DE2-115 has two instances of the same phy, identified in the I/O signal list with "ENET0_..." and "ENET1_..." signal names. The DE2i-150 board has one instance - all "ENET_..." signal names. 

 

You will have to instantiate one instance of the triple-speed mac, exactly as per item 6 in section 3.1 of the Triple-Speed Ethernet paper you sighted. Then, in Quartus, you will connect up the exported top level signals from Qsys to the appropriate DE2i-150 FPGA pins, according to the pinout given in the manual/schematics. 

 

Cheers, 

Alex
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