Hello! I am using TSE(triple speed ethernet) ip core to implement communication bewteen my pc and the FPGA(cyclone IV). But I don't know how to configure the TSE register with verilog. I do read some information from the user guide. For example, here are from the user guide:Base registers to configure the MAC function. At the minimum, you must
configure the following functions:
• Primary MAC address (mac_0/mac_1)
• Enable transmit and receive paths (TX_ENA and RX_ENA bits in the
But I don't know how to realize this configuration in my project with verilog.
Anything can be help!
Thank you for posting in Wired Communities. Further checking inquiries for Altera product should be supported by Altera support, you can contact them at https://www.altera.com/support/support-resources/intellectual-property/interface-protocols/triple-speed-ethernet/ips-inp-tse.html Triple-Speed Ethernet MegaCore Function Resource Center or you may go to https://www.altera.com, select Login or to create a new account, after the complete verification process (via email) you may use the Support section of Altera's website to create a Service Request.
Hope the above information help.