how to implement simple RAW ethernet communication between fpga and pc

[Altera_Forum]

Hi everyone , my aim is to implement a simple system who permits to send data to a PC only using the phisycal layer of the ethernet interface of the board de2/115. Following a tutorial I had built the sistem, but the related software for the nios II processor permits only a loop comunication between the ethernet interfaces of the board. Anyone can help me , for example suggesting a tutorial or posting a code who can works for this project ? 

Thank you

[Altera_Forum]

If you really want to implement a system at the PHY layer, you shouldnt be using a NIOS. You need to read this https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/xcvr_user_guide.pdf 

It wont be simple.  Have you read this for a TCP/IP stack? https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_nios2_tcpip.pdf

[Altera_Forum]

Thank you for your reply, I was reading your second link, there are some tutorial design, but they are not for my board, I`m using a cyclone IV. 

It is possible to migrate a design from cyclone III to cyclone IV ?

[Altera_Forum]

You might need to reinstantiate the IPs in your design from CIII to CIV.

[Altera_Forum]

Ok Thank you .