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LFelt
Beginner
1,469 Views

i210 FLUPD bit set by write to EEWR? / datasheet description for EELOADCTL and EELOADERR

Hello,

I've got an i210 connected to an SoC and for production I'd like to write the external eeprom via PCIe:

- I map the config space and access the IO area via the config space registers 0x98/0x9C

- The semaphore and sync between FW/SW seems to work

- I write the config (0x80 16bit words) to the SRAM and can read it back, checksum is 0xbaba

Triggering the flash write via FLUPD fails: FLUPD is already set to one by the first write to the SRAM?

After the first SRAM write via EEWR, EEC reads: 0x482a00, is this correct?

When will FLUPD be reset? By whom?

Also I'd like some more documentation on two registers:

Chapter 8.4.2 describes EELOADCTL:

This register provides software EEPROM-mode load status.

All bits are RW to FW, RO to host - excepted to bit 12.

Then it gives a short table for bit0 all ohters are reseved, a second, completely different table describes bits 0:32.

In chapter 8.4.5 EELOADCTL is described a second time with a single sentence.

EELOADERR is in chapter 8.4.4 but there's no description of the bits (table missing?)

Can you please provide me the missing/correct tables for these registers?

Best regards,

Lo

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7 Replies
idata
Community Manager
92 Views

Hi Lo2,

 

 

Thank you for the post. I need to further check for you.

 

 

rgds

 

wb

 

LFelt
Beginner
92 Views

Hello,

any progress on this?

Can you please post a correct description of the EELOADCTL and EELOADERR registers?

Best regards,

Lo

idata
Community Manager
92 Views

Hi Lo,

 

 

Apologize for the delay. I still need additional tim to check on this, I will update you once there is update.

 

 

rgds,

 

wb

 

idata
Community Manager
92 Views

Hi Lo,

 

 

What is your CPU model and do you have a Non-disclosure agreement with Intel?

 

 

Thanks,

 

wb

 

LFelt
Beginner
92 Views

Hi wb,

The CPU is a Freescale i.MX6 quad core Cortex A9.

I've got no NDA with intel yet.

Best regards,

Lo2

idata
Community Manager
92 Views

Hi Lo2,

 

 

Thank you for getting back to us. I will further check for your concern.

 

 

rgds,

 

wb

 

idata
Community Manager
92 Views

Hi Lo2,

 

 

Further checking, you need to contact the field application engineer of Intel if you do know one, you also need to have an Intel NDA to receive the eepromARmTool to program the iNVm.

 

 

If you do not have contact with Intel engineer, you may go back to the point of purchase or the system vendor where you got the I210 controller.

 

 

Thanks,

 

wb

 

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