lwip quartus 18.1 arria 10

[Msg06484]

Hi,

I have the lwip core.  I have the sample design for the Cyclone IV E, found at https://github.com/adwinying/lwIP-NIOSII/tree/master/FPGA/software/lwIP_NIOS_II_Example

I am tying to develop this for the Arria10 in Quartus 18.1

I first instantiated the sgdma and found that the lwip does not like that...

I then found that it does like msgdma so I instantiated that, but still there are errors.  Things like - ALTERA_TSE_SGDMA_INTR_MASK and ALTERA_TSE_FIRST_RX_MSGDMA_DESC_OFST

If I am telling the truth I also instantiated on chip memory (RAM) for the dma, and a descriptor_memory ROM, I hope I connected them all properly.

I am the only person in the company on this project right now.  I have access to a corporate tech support at Intel, but we are struggling.

Does anyone know of a sample design that would be more fitting for lwip on Quartus 18 (possibly with arria10)?

Thanks in advance.

[ShengN_Intel]

Hi,

Intel® SoC FPGA Embedded Development Suite link https://www.intel.com/content/www/us/en/software-kit/665453/intel-soc-fpga-embedded-development-suite-soc-eds-pro-edition-software-version-18-1-for-windows.html? got example in ../embedded/examples/software/SoCFPGA-HardwareLib-Ethernet-A10-ARMCC.tar.gz

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Any further concern or update?

Thanks,

Best Regards,

Sheng