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ノイズ対策 PLLの挿入について

TYasu8
Beginner
302 Views

FPGAの同期用のクロックを、PLL(Altera PLL) を通して入力するとノイズ対策として効果はありますか?PLLの入力は24.576MHzで出力も 24.576MHzで考えています。

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1 Reply
Rahul_S_Intel1
Employee
97 Views

Yes,

and also make sure that the input give through dedicated clock pin

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