关于在S10 上做PCIE RC（root complex）

[PYu2]

客户打算在S10 GX上做两个PCIe RC，一个EP。

问一下， 有过在S10上做RC的设计吗，咱们的PCIe 硬核支持RC模式吗？如果硬核支持，管脚是什么样的限制？

如果是软核实现，管脚又有什么样的限制？

[BoonT_Intel]

Hi Sir,

Yes we support Root complex (root port) in Stratix 10 PCIe Hard IP.

See this page for the support feature in all devices (including Stratix 10). You can see S10 is supporting Root port.

https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-protocols/m-pci-express-protocol.html

Regarding the pin limitation, it is depend on how many transceiver channel that you have in your device, you can refer to chapeter: 1.8 PCI Express IP Core Package Layout of document as below.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-s10-pcie-avst-17.1ir1.pdf#page=11

[PYu2]

Hi，

没有看到HIP做RC用时，Perst信号怎么接， 专用的管脚吗？​谢谢！

[BoonT_Intel]

Hi Sir,

Yes, also assign to dedicated NPERST pin of the device. same like native end point