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PTan9
Partner
186 Views

请教使用10AX115S3F45E3SG器件实现4个40GE IP加48个1G/10GE IP管脚分配编译不过问题

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想用72通道的10AX115S3F45E3SG器件实现4个40GE IP加48个1G/10GE IP,但是管脚分配编译不过。以左边6个Transceiver bank计划放下2个40GE+24个1G/10GE IP为例,下面2个bank单独放2个40GE IP可以编译通过(两个IP共享ATX PLL),上面4个bank单独放24个通道的1G/10GE可以编译通过(共享一个ATX PLL),全部放在一起就不行,请问有什么限制?另外我上面这样多个IP共享ATX PLL是否有风险?谢谢。

Best Regards

Penn

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10 Replies
PTan9
Partner
70 Views

另外我也尝试把2个40GE分别用CMU来做TX PLL,也是编译不过。也还试过左边放12个1G/10GE+4个40GE(占用16个10G通道)​,右边放置18+18个1G/10GE,也是编译不过。通常都是卡在Fitter 5%一个多小时,Info (16210): Plan updated with currently enabled project assignments. 也有部分直接报部分通道不能分配。

Deshi_Intel
Moderator
70 Views

HI,

 

The main factor that will affect fitter error would be XCVR channel pin placement and also PLL resource usage.

  • But I can only comment further after I reviewed your design first.
  • Another tip to debug fitter error will be to let Quartus auto fit as much as possible to test out whether it's possible to fit in your user design requirement first on this specific FPGA package
  • Also can you share with me your design QAR file to help me understand the fitter error better ?

 

The main restriction will be user can't use same PLL to support different data rate. (for instance : 1G vs 10G data rate switching)

 

  1. For 1G/10G PHY IP - it required one pair of Tx/Rx channel + 1G PLL (CMU/fPLL) + 10G PLL (ATX/CMU)
  2. For 40G IP - it required four pair of Tx/Rx channel + 10G PLL (ATX/CMU)

 

Thanks.

 

Regards,

d

PTan9
Partner
70 Views

Hi DeshiL,

请问我是否可以把40GE IP和​1G/10G PHY IP种的10G TX PLL使用fPLL来实现?以避开ATX PLL,7个间隔的要求,以及满足可以驱动XN/X6线的跨bank共享需求?因为CMU PLL即要占用XCVR通道,又不能跨驱动XN线。目前10G ATX PLL改为fPLL是能编译通过的,有什么风险吗?

Best Regards

Penn

PTan9
Partner
70 Views

Hi DeshiL,

另外40GE IP 除了TX PLL外,还需要消耗2个IO PLL,一个做MAC TX PLL,一个做MAC RX PLL,这两个是否可以节省?MAC TX PLL可以使用外部的,但是一放到外部,和其它的40GE IP共享,就会报错。

Best Regards

Penn

PTan9
Partner
70 Views

Hi DeshiL,

还有一个问题,我尝试了多个40GE IP勾选了使用外部TX MAC PLL​,会生成clk_txmac_in,我用我的系统的PLL(参考时钟是100MHz)产生一个312.5 MHz驱动他们可不可以?我这么操作,编译是没有报错。就是不知道有没有风险。

Best Regards

Penn

PTan9
Partner
70 Views

Hi DeshiL,

还有如果一定要按照手册上说的,TX MAC PLL的参考时钟要来自于PHY refclk 322MHz,如果我想节省一个IO PLL,那么我是否可以尝试分配在器件左右两边的4个40GE IP,共用一个使用PHY refclk作为参考的TX MAC PLL输出,作为clk_txmac_in的驱动。然后我通过器件外部增加一个时钟buffer,把从同一个322MHz 晶振输出的时钟,通过buffer给到器件左右的收发器bank作为PHY refclk,通过这种方式,保证左右的参考时钟都是同源,用任意一侧参考时钟驱动的IO PLL的输出,能驱动4个40GE IP.

 

 

Best Regards

Penn

PTan9
Partner
70 Views

Hi DeshiL,

工程见附件。除了4个40GE,48个10GE,还有一路4通道的10G BASE-KR. 至于顶层的PCIE X2因为实在放不下没有添加了。​

Best Regards

Penn

Deshi_Intel
Moderator
70 Views

Hi Penn,

 

I can see that you have a lot of questions and doubt.

 

Let's take it into private discussion for better communication.

 

Thanks.

 

Regards,

dlim

 

 

PTan9
Partner
70 Views

Hi DeshiL,

​I will be ok at 4:30 this afternoon.​ Thanks.

Best Regards

Penn

Deshi_Intel
Moderator
70 Views

Hi Penn,

 

I hope everything is clarified and clear to you now.

 

So, I will be setting this case to closure.

 

Thanks.

 

Regards,

dlim

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