The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine.
However, when simulating my design, the PHY can not acheive rx_block_lock.
The waveform shows that, for a loopback pair, the xgmii_tx_data of the TX side is 200_009c_0200_009c, while xgmii_rx_data of the RX side is 100_009c_0100_009c. It seems one 1-bit is missing and hence rx_block_lock is never asserted. The whole simulation went timeout.
From the log there is one warning:
Warning : At time = 3088266ps
Warning : The Nand Delay chain step size is larger than 80 ps, measured step size = 40ps and/or 1050ps
This warning looks fishy and it did not show up when simulating the example design.
Please help. Many thanks.
More info: in my waveform,
rx_cdr_refclk_1 is 322.265625 MHz, as specified by the Reference clock frequency for 10 GbE (MHz) parameter.
rx_pma_clkout is only 78 MHz (it should be 156.25 MHz according to the spec).
BTW, the warning has been solved. I copied tb_top.sv from the example design, where the refclk_10g is 644 Mhz, while in my design, it should be 322 Mhz. After changing refclk_10g to 322 Mhz, the warning is gone. But rx_pma_clkout is 78 Mhz...
The Multirate PHY IP has parameter setting for "Reference clock frequency for
10 GbE (MHz)" where user needs to specify whether you prefer PLL refclk input is 644MHz or 322MHZ
Whatever clock frequency that you provided in test bench design needs to match with the setting in Multirate PHY IP.
Can you double check your Multirate PHY IP setting again ?
Thanks for the clarification.
rx_pma_clkout is derived from rx_cdr_refclk_1. If you have provided correct clock frequency in test bench file then by right rx_pma_clkout should be 156.25MHz.
Can you share with me more info as below ?
0. My rx_cdr_refclk_1 is 322.265 Mhz.
1- Stratix 10, 1SM16BEU2F55E2VG
2- Quartus Pro v20.1
3- VCS 2017
4- I tried Modelsim 10.6 on Windows but it failed to handle long file names. The testbench files provided by the example design have very long file names.
5- Please see the attached
In the example design, I changed the refclk to 322 MHz:
Now, in the example design, rx_pma_clkout becomes 78 MHz and it cannot achive rx_block_lock.
Would you please try 322 MHz for the "alt_em10g32_0_EXAMPLE_DESIGN/LL10G_1G_2_5G_10G" example design?
I am able to duplicate the 322MHz example design sim run failure (rx_block_lock) stay low issue even in modelsim. While sim run with 644MHz setting is fine.
I am now consulting internally within Intel to figure out is this a bug or something that we miss out when using 322MHz setting.
Will keep you posted on status update
Hi @DeshiL_Intel ,
There is a core_pll in models/tb_top.sv that also needs to be changed, as it uses refclk_10g as well.
After modifying this pll, the example design is able to run with refclk_10g at 322 MHz.
Now I'm checking what's wrong with my design...
refclk_10g is used in 3 IP. I made below design changes but Modelsim run still failed.
Below is the modification steps
Thanks. I copied over the newly generated mif file to rtl/reconfig folder. Now, I can see that rx_block_lock asserted high.
Hopefully you can find out what's wrong with your design as well. All the best to your project development.