Hi,I'm using QII 14.0. By using Altera design example files have done simulation and implementation of 10G EMAC- 10G BAse R on Arria V GT fpga board with help of reference documents "Stratix V 10G Ethernet and 10G Base R PHY Interoperability Hardware Demonstration Design". internal loop back is working fine. I want to send the packets from MAC(FPGA) to PC (system). Any suggestions??