10G ETHERNET MAC-10G Base R

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

10G ETHERNET MAC-10G Base R

935 Views

Hi,

I'm using reference design example "10G EMAC-10G Base R" with Quartus 13.1 and Arria V GT Fpga. Simulation works fine. when i do compilation process, in Fitter(place and route) i'm getting Critical warning as below,

Critical Warning (11087): PMA direct channel(s) detected and needs to be constrained based on the guidelines in Arria V Device Handbook Volume 3: Transceiver chapter.

Have attached Pin Assignment of my design.

what could be the reason.?? Also i refered to Arria V device handbook but didn't get solution.

Please help me to solve this Issue.

thanks and regards

Vinod Kumar

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.