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10G Ethernet MAC Design example issue

Altera_Forum
Honored Contributor II
1,023 Views

Hello, 

I'm using Quartus II 14.0. I wanted to simulate the design example for 10G Ethernet MAC ip core. I'm following Altera Document for step by step procedure for 10G E MAC ip core Mega function user guide. when i run the do tb_run.tcl , the modelsim fails to simulate and it gives an error. 

 

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# Top level modules:# altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_mux# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013# -- Compiling module altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux# ** Error: (vlog-7) Failed to open library file "D:/Altera_working/altera_eth_10g_mac_xaui/altera_eth_10g_mac_xaui/simulation/mentor/libraries/rsp_demux/altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux" in read/write/execute mode. 

# # No such file or directory. (errno = ENOENT) 

# ** Error: ./..//submodules/altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux.s v(99): Verilog Compiler exiting# ** Error: D:/altera/14.0/modelsim_ase/win32aloem/vlog failed. 

# Error in macro ./tb_run.tcl line 32# D:/altera/14.0/modelsim_ase/win32aloem/vlog failed.# while executing# "vlog -sv "$QSYS_SIMDIR/submodules/altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux.s v" -w..."# ("eval" body line 5)# invoked from within# "com" 

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what could be the problem.?? Do i need to set ENV_VARIABLES for modelsim..? 

Please help me. 

 

thanks & regards 

Vinod Kumar
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
96 Views

Which design example that you are using? Is it QII generated or from Altera web?

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