FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5984 Discussions

10G Ethernet MAC Design example issue

Honored Contributor II


I'm using Quartus II 14.0. I wanted to simulate the design example for 10G Ethernet MAC ip core. I'm following Altera Document for step by step procedure for 10G E MAC ip core Mega function user guide. when i run the do tb_run.tcl , the modelsim fails to simulate and it gives an error. 



# Top level modules:# altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_mux# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013# -- Compiling module altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux# ** Error: (vlog-7) Failed to open library file "D:/Altera_working/altera_eth_10g_mac_xaui/altera_eth_10g_mac_xaui/simulation/mentor/libraries/rsp_demux/altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux" in read/write/execute mode. 

# # No such file or directory. (errno = ENOENT) 

# ** Error: ./..//submodules/altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux.s v(99): Verilog Compiler exiting# ** Error: D:/altera/14.0/modelsim_ase/win32aloem/vlog failed. 

# Error in macro ./tb_run.tcl line 32# D:/altera/14.0/modelsim_ase/win32aloem/vlog failed.# while executing# "vlog -sv "$QSYS_SIMDIR/submodules/altera_eth_10g_mac_xaui_eth_10g_design_example_0_e th_loopback_composed_mm_interconnect_0_rsp_demux.s v" -w..."# ("eval" body line 5)# invoked from within# "com" 



what could be the problem.?? Do i need to set ENV_VARIABLES for modelsim..? 

Please help me. 


thanks & regards 

Vinod Kumar
0 Kudos
1 Reply
Honored Contributor II

Which design example that you are using? Is it QII generated or from Altera web?