Hi all,I am trying to create a 10GBASE-R design using Qsys the same way as in the Transceiver toolkit examples provided by Altera for Custom and LowLatency PHY IP cores (on page On-chip Debugging Design Examples). My device is Stratix IV GT and the board is EP4S100G2F40I1. I am stuck with several issues like below: 1, I need to include a pattern generator/checker. But the xgmii sdr interface is one 72-bit symbol/beat, while the ST data pattern generator/checker have either 8-bit or 10-bit symbols and support output of either 32-bit or 40-bit wide data. And the ST Data Adapter does not help to solve this mismatch. So, I changed to use the ST test pattern generator/checker instead. But I do not know how to feed clock as they do not have separate clock for output interface. 2, It is stated in Transceiver PHY IP core user guide that the 10Gbase-r is not supported in Qsys and recommended to use Megaziward instead. However, I found a way to include the core in the Component library. I wonder if it is ok to create the design in Qsys or I must do that with Megawiward. If anyone can give me a clue for my issues. Thank you for reading and any suggestions or comments are highly appreciated.
>1, I need to include a pattern generator/checker. >But the xgmii sdr interface is one 72-bit >symbol/beat, while the STI don't quite understand your problem. But hopefully some information may help. Regarding this item, the 72 bit is consisting of 64-bit data (bit 63:0), and 8 bit control. Break the 64 bit into 4x16 bit chunks, then you can use the test pattern design example from Altera (looks like you have this already) with some modifications by configuring their 10bit design into 16 bit. You need to use the 4 channel version to get 64 bits. You need to change the timing adapter and data adapter in the design example to match the outputs/inputs from your Transceiver. This can be done in Qsys, and Edit the instantiation to 2 symbol per beat (times 4 of course). Hope that helps.