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Hi All,
Does anybody know why avalon_st_tx_ready de-asserted in the middle of the packet transfer? Attached a capture of signal tap. I can see a missing data on the pc that receive this packet. the missing data is correlated with data transmitted while avalon_st_tx_ready de-asserted. ThanksLink Copied
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That means the receiver cannot receive the data. If the data isn't held during this period then it will be lost.
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The data is transfered to the PC.
Do you mean there is a problem with the PC's 10G card?- Mark as New
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What is the ready latency parameter on the ethernet IP core?
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I am sending a 124Byte packet every 10 sec. I don't see how it can be a latency problem.
What do you mean by pointing ready latency parameter? ( "The ready latency on these interfaces is 0 and the MACexpects the empty signal to contain a valid value."----10-Gbps Ethernet MAC MegaCore Function User Guide----page 7-4)- Mark as New
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If the ready latency = 0, what does the data change when ready is low?
The length of the package from the (very low resolution) picture you sent appears to show 15 transactions, when a 124 byte package would require 16 transactions with tx_empty set when end of packet is asserted. Please post a better picture with more signals Next question - did you simulate this design before putting it in the FPGA?- Mark as New
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Without the code in the FPGA design, I dont know what you want me to do.
The FPGA appears to be not working properly.- Mark as New
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does anybody else has an idea what can be the problem.?????
-- The problem can be seen also in simulation- Mark as New
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If the problem is also in simulation, then it is clearly a problem with the fpga logic that generates the packets
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In Signal Tap : the packets are transmited by an external PC (was validate and works fine).
In simuation : the same packets are transmited by a test bench. The fpga logic is ALTERA's IPs (MAC & PHY). no logic was added. Do you think altera has problem with this IP?- Mark as New
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n Signal Tap : the packets are transmited by an external PC (was validate and works fine).
In simuation : the same packets are transmited by a test bench. The fpga logic is ALTERA's IPs (MAC & PHY). no logic was added. Do you think altera has problem with this IP?- Mark as New
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I think it's highly unlikely a problem with altera IP - ethernet cores are very mature.
You could try raising a ticket with them Without you posting the design - there is little we can do to help.- Subscribe to RSS Feed
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