Hi, I am working on doing background subtraction with DE2 development board and I want to do a noise filtering using the median filter 2D megacore function which comes with the quartus II 11.1sp1 Web Edition. Somehow, I couldn't get the things work. Thus, I have a few questions as below and really hope if there is someone who can help me on this cause I am already lack behind of the development progress.1. Does it need a specific license to generate the median filter 2D file(verilog) properly? 2. How does the module really works with its input and output signal? There is an output signal DIN_ready which I suppose it should signifies the module when it is ready for input but somehow it is always 0. 3. I got the median filter 2D verilog file generated but it starts with a comments GENERATION: DEFERRED. Is this normal? The comments are as shown below. // megafunction wizard: %Median Filter 2D v11.1% // GENERATION: DEFERRED // synthesis translate_off Really there is anyone who can help me on this. Thank you in advanced!
the VIP suite cores are a bit "weird", the source HDL doesn't actually fill up with code, just comments for something that's generated during compilationare you able to compile successfully? if not, see the errata, there's a known issue about generating and compiling the VIP Suite cores on Windows Vista and 7. the work around is running Quartus as Administrator to generate and compile the VIP Suite cores
Thank you for replying thepancake :)Anyhow, I am able to generate and compile it without any errors but it doesn't seem to be working when I connect the input and output signal. It seems like the median filter core function never get "ready" to accept any input? output din_ready; input din_valid; input [9:0] din_data; input din_startofpacket; input din_endofpacket; input dout_ready; output dout_valid; output [9:0] dout_data; output dout_startofpacket; output dout_endofpacket; I suppose we should first get a "din_ready" signal from the core function first before we input any data to it based on the input and output signals of the core function. Correct me if I am wrong or if there is any steps need to be taken care before using it? Thanks alot!:) Regards, PS
You will need to make sure that your input conforms to the Avalon-ST Video data format, as specified in the Video & Image Processing Suite User Guide (you can find this online). The output will also use this standard. Both the input and output use a 1 cycle ready-latency handshake protocol where the input valid may only be high on clock cycles that come 1 clock cycle after the ready was high.