3D RAM EMIF IP support

[ushermark]

Hello.

Making a duplicate of the topic based on this one.

We are currently using Intel Arria 10 FPGA for our projects. For designing and programming it we have Quartus Prime Pro v21.1.0 Build 169.

Does it support 3D memory technology and 128GB+ external RAMs? If not, is there a chance of supporting such memories in newer versions of Quartus Prime software?

Best regards,

Mark

[AdzimZM_Intel]

Hi Mark,

Does the "3D RAM" here give a same meaning to 3D stacked die?

For Arria 10 device, the 3D stacked die is not supported by the EMIF memory controller.

This feature is only available in Stratix 10 and Agilex 7 devices.

The memory density is possible for 128GB because the memory controller can support data width up to 144bits and 4 ranks.

You may refer to this link for features available in Arria 10 EMIF memory controller: https://www.intel.com/content/www/us/en/docs/programmable/683106/21-1-19-2-0/hard-memory-controller-features.html

Regards,

Adzim

[ushermark]

Hello Adzim,

I apologize for a delayed answer.

Could you provide an example project with 3D stacked die EMIF either for Stratix 10 or Agilex 7?

Best regards,

Mark

[ushermark]

In addition to my message above, is there a possibility(workaround) available for Arria 10 to use 3DS EMIF IP?

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

[AdzimZM_Intel · Accepted solution]

Hi Mark,

Yes sure I can share an example design with 3DS EMIF interface targeting Stratix 10 device.

It's unfortunate that the 3DS device does not support in Arria 10. The hard memory controller does not support 3DS and Chip ID bits.

Regards,

Adzim

[AdzimZM_Intel]

Attaching example design.

[ushermark]

Hello Adzim,

Thank you for the example design.

I think I got all required information so far.

Thank you for your support.

Best regards,

Mark

[AdzimZM_Intel]

I'm glad that your question has been addressed, I now transition this thread to community support.

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

Thank you.