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Altera_Forum
Honored Contributor I
724 Views

64 bit Avalon MM to ST FIFO for PCIe 3.0 IP core

Hello everyone 

 

I am working on integrating the PCIe3.0 IP core from Altera with my existing application. So far we have been using SFP interface to communicate with the host and we would like to use the PCIe interface now. 

 

My current application has 64 bit Avalon ST interfaces for data. But the BAR interfaces are Avalon MM with 32 bit data. When I tried using a FIFO with MM on one side and ST on the other I was not able to change the data width from 32 bits. 

 

Is there a reason why we cant have 64 bit Avalon MM to ST FIFOs? 

 

How can I solve this problem? Is it feasible to make a custom FIFO by looking at the generated code for the 32 bit version? 

 

Or can I clock the 32 bit FIFOs with twice my application clock frequency? This seems to be easier+quicker(development) but are there any drawbacks of this approach? 

 

Thank you very much in advance. 

 

Ankit Pradhan
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2 Replies
Altera_Forum
Honored Contributor I
20 Views

I believe you are using Stratix V FPGA, correct? 

Stratix V PCIe core should be able to support 64-bit data width for application layer to Transaction Layer interface.
Altera_Forum
Honored Contributor I
20 Views

Hi skbeh 

 

Thanks for your response. I am using Arria V FPGA, but I believe the example project(Avalon MM interface for PCIe with DMA) that I'm using works for both, with the exception of some Quartus settings. 

 

The problem I have is to convert from BAR's MM interface to an ST interface which is 64 bits wide. Apparently the MM to ST FIFO can only have a 32 bit data width. 

 

By the way, what makes you say that 64-bit data width is supported? Although I select the BAR to be 64 bits wide, after looking at its block view for signals, only the address width changes to 64 bits and the data width remains 32 bits wide. Please see the attachment. 

 

Is a 64 bit address bus ever useful? Are we ever going to address that much memory? 

 

Thanks 

Ankit Pradhan
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