Hi,I am using QSYS and am trying to transfer the contents of a memory component to a custom component with a DMA. Both memory and custom component have a data bus width of 64 bit, and the DMA is configured to transfer DWORDS. And yet the transfers only work partially. A look at what SignalTap picks up before and after the DMA module shows that all 64 bits are read from the memory, but only the lowest 32 bits of this data makes it to the component with the upper 32 bits being set to zero. The Embedded Peripherals IP User Guide states that "Currently the Altera-provided drivers do not support 64-bit and 128-bit DMA transactions." but this should not matter as I have bypassed the HAL drivers and am writing to the DMA registers directly (with the settings for DWORD transfers). May the problem be that I don't have byteenable signals on the custom component? (not that this should matter IMO) I am at a loss as to what is not working correctly here. Many Thanks, Josef
--- Quote Start --- A look at what SignalTap picks up before and after the DMA module shows that all 64 bits are read from the memory, but only the lowest 32 bits of this data makes it to the component with the upper 32 bits being set to zero. --- Quote End --- I don't have a direct answer to your problem, but I wanted to mention that since you're already setup with SignalTap, what you actually want to look at is the Avalon-MM Master port from the DMA and then the Slave port within your component. In other words, the before/after of all the Qsys-generated connections including any adapters it inserted. You can also figure this out by skimming the generated code, but in your case maybe it's faster to just examine it live. If you see the DMA posting a properly formed 64-bit write, but your component only sees the 32-bit write, you know the issue is with how Qsys perceives your component (byteenables or otherwise) and the issue is not with your register settings for the DMA.
I have found the problem and I'm a little embarrassed about it. I had copied and pasted the source files of another component and had changed the name everywhere except for the module name in the Verilog file. As a consequence, everytime I compiled the system the other module, which only had a 32bit interface, was used instead...