64-bit Qsys PCIe Bus Master Address Register Programming
I'd like to clarify description of the page registers provided in table 6-17 on page 6-10 of the IP Compliler for PCI Express
User Guide.The combine upper bits and lower bits of the Avalon to PCI Express address map looks like PCI Express address shown on Fig. 4-12 on page 4-24.N is number of bits that represent the page size. Let me give an example. Let assume that we define 4 MB page (22 bits) to address memory allocated by the system with 64 bit address 0xffff_7123_45c0_0000. The low part of the content of the page translation register will be 0x45c0_0001 and the upper part will be 0xffff_7123. By the way the page size bits size part of the register (low 22 bits in the example above) are not readable.