FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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640x480x8p Video Mirror

Altera_Forum
Honored Contributor II
‎11-24-2010 02:33 PM
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We have been working on a video mirror block to slip into the Altera Video IP chain and are finding it not nearly as simple as had been suggested here on the forum. 

 

Here then are the pieces we are working on ... We believe we get one frame through and then the next frame gets out of sync. 

 

We're going to try a few things today but if anyone would like to help offer useful suggestions or assistance we would be very greatful. 

 

At some point we will make it more capable and parameterized though I can't tell you when exactly that will be. 

 

Thanks in advance 

 

Tom
good_sim_vga_mirror.zip
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Altera_Forum
Honored Contributor II
‎11-24-2010 05:09 PM
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i suggest writing a core that can simply pass video data first. getting the Avalon Streaming ready latency = 1 protocol correct is the most difficult part. after you are able to pass a real video stream, adding the mirroring function should be fairly straight forward 

 

i spent some time getting the ready latency = 1 working in the VIP control decoder: 

 

http://www.alterawiki.com/wiki/vip_control_decoder
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