A/D's on Stratix Dev PCB get HOT!!

[Altera_Forum]

I have noticed that the Analog Devices A/D converters (AD9433) on my Stratix EP1S80 Development Board get very hot, very quickly. This occurs all the time, even when they are not being used. I cannot place my finger on these chips any longer than a couple of seconds. 

 I have two boards and the A/D's get hot on both. One of them was brand new. When I first plugged the DC supply in, without loading any code or doing anything at all, the A/D's get hot.   And after I program the FPGA, it seems the A/D's run even hotter! Even when the A/D's are not included in the programs application.   I suspect this is occuring on all of these boards but I don't think they should run this hot all the time? It must shorten their lifespan considerably? Could this be a design flaw of some kind? Is anybody aware of a fix?   Thanks

[Altera_Forum]

What's the setting for unused pins in your design? Configuring unused pins as output (the default setting with previous Quartus versions) would short the ADC outputs.

[Altera_Forum]

Actually, its default even in current Quartus version. I've got ~4 hours of headache why my design doesn't work, until a co-worker showed me that option. What a dumb default option, when it is possible to burn all the hardware attached!

[Altera_Forum]

Hi, 

 I'm a FPGA beginner and a EE student and I bought an used Stratix EP1S80 DSP Development Board which came with no DSP Dev Kit CD-ROM (missing the labs, design examples and board supportive files).  Do you know how can I download this CD-ROM or purchase it? This is a 2004 product and I'm using for FPGA learning purpose.  Thanks, Rob.

[Altera_Forum]

--- Quote Start ---  Hi,  I'm a FPGA beginner and a EE student and I bought an used Stratix EP1S80 DSP Development Board which came with no DSP Dev Kit CD-ROM (missing the labs, design examples and board supportive files).  Do you know how can I download this CD-ROM or purchase it? This is a 2004 product and I'm using for FPGA learning purpose.  Thanks, Rob.  --- Quote End ---    Try looking here ...  ftp://ftp.altera.com/outgoing/devkit/  (Its not a well organized folder, but perhaps there is something there).  All you really need is the schematic for the board, so that you can generate a constraints file for the FPGA pinout. The examples are not generally of much use. If you want help, just ask here on the forum and you'll get better examples. I don't have the kit you are talking about, but if you find the schematic, I can help you get started.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Thanks a lot!  I found the kit CD-ROM in the folder you pointed out: devkit/Stratix_DSP_Pro-v1.3.0_CD.zip  The schematics PDF is available after installing this kit. Now I need to figure out how to create an universal constraint file with all FPGA pinout.  Thanks, Rob

[Altera_Forum]

--- Quote Start ---   I found the kit CD-ROM in the folder you pointed out: devkit/Stratix_DSP_Pro-v1.3.0_CD.zip   --- Quote End ---  Great.    --- Quote Start ---   The schematics PDF is available after installing this kit. Now I need to figure out how to create an universal constraint file with all FPGA pinout.   --- Quote End ---  Here's what I do. Look for a design example in the kit, one that uses all or most of the pins on the FPGA. Open the .qsf file for the project, and you should see the pin assignments as 'set_location_assignment' lines.  Copy all those lines to a new file. Use an editor and keep only the pin name and the pin number.  Look at the attached file (rename it pinout.tcl). You'll see that this file contains Tcl commands to create a Tcl variable called 'pin'. The variable is actually a Tcl array, with the pin names as every element in the array. The 'value' of each element is the pin number. Down the bottom of this file, there is a Tcl loop that converts the Tcl array into Quartus pin assignments. I personally find this easier to maintain, but you could just as easily have 'set_location_assignment' commands on every line.  You can source this Tcl file from Quartus and it will setup the pin assignments for every design that uses this board. The caveat is that your top-level VHDL or Verilog entity should have all the same signals defined, otherwise you get warnings about invalid pin assignments.  Once you have the first version of your pinout file, go through the schematic and make sure every pin is correct, and that all pins used have an assignment.  Have fun!  Cheers, Dave

[Altera_Forum]

wonderful! thanks a lot!