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I have only ever used a PLL within an FPGA to multiply, or divide, the incoming clock frequency, or phase shift the incoming clock. I have never used a PLL if the design only has one clock frequency.
A reviewer of my code has suggested that it is good practice to clock the internal logic from a PLL, not the external crystal oscillator clock input. Is there advantage to doing this?
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Hi,
In the FPGA, the clock must be connected to the dedicated clock input pins [clk0p/n, clk1p/n..... ] to get the external clock to the clock network of FPGA. But usage of PLL is not necessary unless you want to have some kind of clock synthesis.
However, the input clock connected to dedicated pins can be used in the design without any PLL.
module test (
input wire clock,
input wire reset,
output reg toggle
);
always @ ( posedge clock) begin
if (reset) begin
toggle <= 1'b0;
end else begin
toggle <= ~ toggle;
end
end
endmodule
With Regards,
HPB
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Hi Fergus Robertson
PLL provides synchronization between external clock and internal clocks. A slight change at external clock does not vary the PLL frequency.
When a PLL locks onto the input frequency, there is a limited variation of that signal at the output. This is good for jitter reduction and clock skew control of the design.
Thanks.
Eng Wei
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Hi Fergus Robertson
Let me know if you have any further request on this topic before we go ahead to close the ticket.
Thanks.
Eng Wei
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Hi Fergus Robertson
We do not receive any response from you to the previous feedback that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Eng Wei.

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