Hello all,Recently I used a dcfifo mega core to buffer datas, I found there're 2 signals for usedwidth : rd_usedw and wr_usedw I don't understand the difference between these two signals. Why we need two signals to both read and write side? Do the read and write side share one fifo or do they cut the fifo into two parts, For example, we have a dcfifo with a depth of 1024 words, does it mean 512 words for read and 512 words for write? thx to advance
Are you looking at the usedwd value in the read clock domain or write clock domain? You want to choose the right one so that you can safely capture it. (If you took wr_usedw and analyzed it in the read domain, you will read the wrong data because the clocks aren't synchronous).
--- Quote Start --- I found there're 2 signals for usedwidth : rd_usedw and wr_usedw I don't understand the difference between these two signals. --- Quote End --- A dual-clock FIFO has two clock domains, the write clock domain (which uses wr_usedw) and the read clock domain (which uses rd_usedw). This is much clearer if you use Modelsim to simulate your components. Please see this thread for a zip file containing simulations of both scfifo and dcfifo components: http://www.alteraforum.com/forum/showthread.php?t=38988 Cheers, Dave