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Partner
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A10 加载问题

主芯片是A10 FPGA,配置芯片为MAX10,和一片MT28EW01GABA1LPC并口flash进行FPP x16加载,不过在加载过程的测试发现,DCLK的波形有很大一部分时间都是一个占空比不是50%的频率为25Mhz的方波,等到配置的结尾阶段时钟会变成一小会100Mhz,请问会这样吗?

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Employee
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Hi,

 

The DCLK will be around 100Mhz during configuration and stay at 25Mhz when it is idle. Do you face any issue during configuration?

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