Can someone help understand how to exercise the AVMM interface of the DDR4 hard memory controller in Arria10 device? I am using the Hard PHY + Controller.
It would be great if there is a timing diagram somewhere which can help me understand the sequence of operations needed to write and read.
I am using a Micron DD4 memory component/chip (it's 64Meg x 16 x 16 Banks x 1 Ranks).
Appreciate any help I can get.
Thank You in Advance!
For the timing diagram and AVMM specification, you can refer to Avalon Interface specifications. For Avalon Memory-Mapped Interface, you can refer to this chapter.
You can see on this chapter, it explain the details of each avalon mm signals and there is timing diagram for clearer understanding.
At the same time, you can generate the example design of the DDR4 IP and run simulation. On the simulation, you can check the traffic pattern of the avalon mm interface.
To run simulation of the example design, refer to this chapter of the external memory hadbook:
Hope this helps.
Thanks for the response. I have seen the links you mentioned.
My question might be more naive; let me ask again with some details: I am running the core at quarter speed. On the AVMM side I see 128bit data interface. My interface to external memory is 16bits. Does this mean that for efficient use of the memory interface, I need to always write/read 128-bit wide data? I am trying to understand what happens if I only use the lower 32-bits? How do I manage the byte_enable and burst_count? I think having some example or timing diagrams on the use of the AVMM interface specifically for EMIF would be very helpful.
If anyone can explain me this (even in English); I will really appreciate it. Warm Regards!
The best way to get started is to generate the example design from the IP parameter editor based on your IP settings. Make sure to include the creation of the traffic generator to see an example of how you'd hook up your user logic to the controller.
As far as your data width is concerned, it's always best, if possible, to match your master interface's width to the width of the slave interface. That way, width adapter logic is not needed. So if the slave side is 128, a 128-bit master might be most efficient. However, if the master is narrower, logic will be added to automatically combine multiple accesses together.
Byte enables would really only be absolutely required with a narrower master performing writes to make sure the appropriate bytes are being written to. Other than that, byte enables would be handled automatically in the generated interconnect. Burst count is used if you plan on locking the master to the slave for multiple read/write commands in sequence.