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[A10 PCIe AVMM] How to implement the customer MSI to Host, while Disable READ/WRITE DMA Done MSI

JET60200
New Contributor I
184 Views

HEllo Expert,

 

We are using "Arria10 PCIe AVMM IP" to transfer data between FPGA and the Host,  and

 it works as expect. 

 

Now we need to implement a customer MSI , so we enable "Export MSI/MSI-X conduit interfaces"  in AVMM IP setting, thus we could implement our customized MSI Event to Host. It works as well.  

 

But the problem we r facing is : each time when AVMM “READ/WRITE” DMA transfer completes, we saw there'r so many  "MSI interrupt to the Host ",  that MSI I believe  comes from DMA Internal Descriptor Controller (dcm_master),  because in “ug_a10_pcie_avmm_dma.pdf”,there mentiones

 7. The Descriptor Controller updates the status of the descriptor table in system
memory.
8. The Descriptor Controller sends an MSI interrupt to the host.
"

 

   But In our case, “DMA Completion MSI ”  is un-useful actually,   since so many those Completion MSI to Host,  may drop the Host Performance.  We'd like to disable this MSI.

How can we "DISABLE The DMA Completion MSI "at all , while still keeping our customized MSI event to Host ?   

 

Any suggestion ?    Thanks a lot  

 

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2 Replies
SengKok_L_Intel
Moderator
167 Views

Hi,


The MSI interrupt is generated from the internal Descriptor Controller and then send to TXS port. There seem like no option to disable it. However, you may create a custom component before the TXS port to detect and drop the MSI message that comes from the descriptor controller if this is NOT necessary.


Regards -SK





SengKok_L_Intel
Moderator
152 Views

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