As shown in SigTap snapshot below, there is an extra pulse of app_nreset_status at sample 61. When this happens, the PCIe device does not enumerate correctly in Windows.
I also have a dump of raw data values for capture below if that helps.
Any ideas what could cause this extra reset to be issued?
May I know what is the speed and link width you are trying to achieve? Could you check if the power supply (VCCR_GXB) is set correctly in the Assignment editor and measure the power supply (VCCR_GXB) supplied to FPGA board is matched with voltage set in the design setting?
You may set the assignment using the pin planner or assignment editor
For Pin Planner
- Right-click on a blank area in the All Pins list and select Customized Columns
- Select VCCR_GXB / VCCT_GXB Voltage from Available Columns and click the> button
- Make sure it is added to the All Pins list and select the transceiver pin voltage you want to change
■ For Assignment Editor
- Register the corresponding XCVR pin name in the To field
- Select VCCR_GXB / VCCT_GXB Voltage in the Assignment Name field
- Select the voltage of the corresponding XCVR pin
From the Fault Tree Analysis (FTA) for Arria 10 PCIe Link Up Issue
https://community.intel.com/t5/FPGA-Wiki/FTA-PCI-express/ta-p/735993, I believe you are at Is rx_std_signaldetect asserted (Hypothesis 4). Can you try the suggestions in FTA_Table_View (No 4)?
If the suggestions in the FTA are not helpful, could you try to run at lower speed and see if this is a problem running at Gen3?
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