A10 PCIe SR-IOV supported tag + bandwidth

[PPham3]

Hi all,

As mentioned in

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-a10-pcie-sriov-14.1.pdf

the supported number of tag is 256 but there are only 2 options ,32 and 64. How can I make it up to 256 ( 8 bit tag)?

By the way, I'm using SRIOV gen 3 256bit stream interface. The maximum bandwidth I can get for rx stream is around 49 Gbps but only around 35 Gbps for TX stream. is that the limitation of the hard IP? after streamming higher bandwidth, the tx_st_ready is deassert forever.

Thanks all.

[SengKok_L_Intel · Accepted solution]

Hi PPham,

By referring to the newer version of document, I don't see the tag is 256 anymore.  32 or 64 should be the right one to support.

Here is the user guide: 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

Regarding to the bandwidth, It seem like the FPGA can't write data to host fast enough? You may increase the payload size, or longer burst mode. Beside, the host may not return credit back to HIP fast enough where need to improve the host processing capability.

Regards -SK

[PPham3]

Hi SK Lim,

so what if HW running out of tag and roll-over?

[SengKok_L_Intel]

256 tag value (8 bits) is optional. If you did not enable the "extended tag field"​, the tag values by default is only 32 (5 bits).

I hope this help.

Regards -SK