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ALM structure

ymiler
Employee
365 Views

Hi 

 

I implemented AND gate and  sample it by FF :

 

Code :

 

wire b,c ;

reg a_sam;

 

always @(posedge  clk)

         a_sam <= b && c;

 

When the Fitter (finalize)  step is finised I opened the Resource Property Viewer and I got the following :

 

ymiler_0-1674202443596.png

 

ymiler_1-1674202721089.png

As you see, the Quartus identified  the AND gate ( F0 & F1 LUT Qquation !a & !d)

 

I have some questions :

1) Why  the mask value 55 appropriate to  AND logic gate ?

2) Why do we need to use F0 and F1 for AND logic gate   ?

3) How can I interpret the mask value ?

 

Yishay

 

 

0 Kudos
8 Replies
ShengN_Intel
Employee
305 Views

Hi,


F0 and F1 are lookup table (LUT). A lookup table (LUT) that implements an arbitrary Boolean function of N inputs is often referred to as an N-LUT check this document https://www.intel.com/content/www/us/en/docs/programmable/683152/22-4/lookup-table-lut.html.

Based on the truth table of the LUT's function http://www2.informatik.uni-freiburg.de/~feiten/teaching/floorplan_ex/tutorial_3.htm, with the LUT Equation !a & !d you'll get LUT Mask of 0000 0000 0101 0101 (0055).


Thanks,

Best Regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


ymiler
Employee
283 Views

Hi Sheng,

 

Thanks for you reply ,

 

Now I'm understanding the mask formula .

 

But , the code was : 

always @(posedge  clk)

         a_sam <= b && c;

Why do the equation defined as :   !a & !d  - I didnt write "not" to theses wires ?

 

In addition , 

Why Quartus use 2 LUT's to implement  simple "AND" gate  ? how does MUX  beaviour ? What is the "select" value ?

ymiler_0-1674982350469.png

 

 

 

ShengN_Intel
Employee
256 Views

Hi,


Check the links below where ALM operated in Normal Mode:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/normal-mode.html

https://www.intel.com/content/www/us/en/docs/programmable/683699/current/normal-mode.html

Note: The Quartus® Prime Pro Edition Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.

The LUT Equation also varies with MLAB cell location and device type.


Thanks,

Best Regards,

Sheng


ymiler
Employee
248 Views

OK

 

But , Why Quartus use 2 LUT's to implement  simple "AND" gate  ? how does MUX  beaviour ? What is the "select" value ?

ymiler_0-1675102861499.png

 

Yishay 

FvM
Valued Contributor I
239 Views
Hello,
the doubled LUT makes no sense at first sight. The effect is, that logic output is the same for both selector states. One would expect that the result can be achieved easier.
Which FPGA family are we seeing here?
ymiler
Employee
234 Views

Quartus Prime version 22.3

Device Family Stratix 10

Device 1SM21BHU2F53E2VG

ShengN_Intel
Employee
222 Views

Hi Yishay,


Top-up to the previous post, check this link https://www.intel.com/content/www/us/en/docs/programmable/683699/current/normal-mode.html:

Normal mode allows two functions to be implemented in one Intel® Stratix® 10 ALM, or a single function of up to six inputs. (Means combination of two LUTs or one LUT with 6 inputs)

The following figure (check the pic in the link) shows a combination of different input connections for the LUT mode.

The Intel® Quartus® Prime Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource use by setting location assignments.


Check this link https://www.intel.com/content/www/us/en/docs/programmable/683699/current/alm-output.html:

The following figure shows the Intel® Stratix® 10 ALM connectivity. In the Intel® Quartus® Prime Resource Property Editor, the entire ALM connection is simplified. Some routings will be routed internally by the Intel® Quartus® Prime software.

The "select" value is datae. These are so far I can find based on document.


Thanks,

Best Regards,

Sheng


ymiler
Employee
188 Views

Hi Sheng,

 

Can you explain please why I dont succeed to change the F0 & F1 masks in the attach ALM ?

ymiler_1-1675764497391.png

 

my tcl includes the command : modify_lutmask -to eco_sig_1_cZ~0 -mask 0x00000000FFFFFFFF

 

after ECO processing I get the following result :

" Error(19796): Atom 'eco_sig_1_cZ~0' (atom id: 2928): Oterm DB_OPORT_COMB_OUT : 0 depends on unconnected iterm type DATAF

There is no DATAF in the Resource Propery Viewer ??

Yishay 

 

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