FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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ALT_LVDS TX, RX and DDR

GLees
New Contributor II
798 Views

ALT_LVDS_TX and ALT_LVDS_RX appear to be designed for SDR operation.  Can they be used for DDR?

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FvM
Honored Contributor II
790 Views
I'd say yes, the only difference is how you interprete the relation of clock and data. In fact, the IP uses DDR registers.
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GLees
New Contributor II
781 Views

Yup, got it.  I've been playing around and now see how to make it work.  Thanks.

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AdzimZM_Intel
Employee
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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