For my Cyclone IV E project, is it possible to manually create a ALTDDIO_OUT instance with a width of 1024.At present, the ALTDDIO_OUT version 10.1sp1 Megafunction wizard only allows selection of bit widths up to 256 bits. So I was wondering if it is possible to manually change any files to increase this to 1024 bits. Thanks Ian
I am a bit bewildered what sort of pcb will have 1024 (possibly pairs) of signals just for data !!! Are you sure this is what you are after ? The general trend is to lower pcb density by moving towards serial side of processing.Remember also you can use serdes to do equivalent work as ddio
Thanks for the quick reply. You may be right about am I asking the correct question as I am very new to HDL and Altera devices and tools. I will explain further what I am trying to do.I want to transfer a source-synchronous data packet between two Cyclone IV E on different boards. The data packet is 1024 bits and only needs to transferred every 50us or so (approx 20Mbps). Cyclone IV GX devices seem completely overkill as the SERDES runs at 600Mbps minimum and are too expensive for my application (and only come in BGA which is not suitable for our production line). What I was trying to do was use DDR clocking on the output data line. I was looking at the Shared Material article in the forum on Implementing a Source Synchronous Interface between Altera FPGAs v2.0 (sorry the forum won't let me have a link as I am too much of a newb) for inspiration and wondering how to implement.
If I understood you, you got a serial stream of 1024 bits per packet (20Mbps) to be sent from one device to another. Just send it with its clock and data valid. There is no indication you need DDR approach.
Transferring this packet in parallel seems a waste of resources, especially at this speed.You could have a look at a serial LVDS interface instead. Have a look at the ALTLVDS megafunction. It could be easier to split your packet in words of 32 or 8 bits too.
Thanks for the comments.I was looking at DDR since the signal needed to travel more than 2m and was looking at reducing the source-synchronous clock frequency for power reasons (since operating off battery and it had to go to transmit to approx another 100 boards with 100 receivers in a multidrop LVDS senario). Also lower clock would give lower EMC. But I have decided to drop DDR for now (stick with SDR) as simplier. Ian