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Altera_Forum
Honored Contributor I
907 Views

ALTGX on Cyclone IV GX

Hi, 

 

i hope any one replay to this.... 

i would like, to implement the transceiver interfaces on the Cyclone IV and if i do this an connect the Transceiver interfaces as an Loop on the Board, i have a problem. When i'm write the number "1" to the port i read back the number 32415 or something similar when i'm read back this with "& 0xff" i become the number 97 back ? why ?  

I think i have problems with the Clock inputs in the Design, i have attached a picture from the .bdf and the Read and Write program form Nios II. 

 

Thanks in advance for you Help... if you need any other information about this project, pleas tell me this ... 

 

------------------------------------------------------------------------ 

 

Hi, 

 

i'm back... i have found a solution for my problem, the timings of the reconfiguration block was to slow. 

 

But i have a second prob jet, and this is, when i'm send the number 1 i read back 256, when i'm sending the number 2 i read back a 512... have any one a solution ? 

 

write --> read 

1 --> 256 

2 --> 512 

3 --> 768 

4 --> 1024
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2 Replies
Altera_Forum
Honored Contributor I
45 Views

Hello, 

 

from your screenshot it looks like you are using a 25 MHz clock? To my knowledge, the minimum pll_inclk for the ALTGX Megafunction is 50 MHz (and should be connected to one of the dedicated, differential clock inputs).  

 

At least for my Cyclone IV GX project, the MegaWizzard reports an error when an input frequency of less then 50 MHz is configured.
Altera_Forum
Honored Contributor I
45 Views

Hello tkxapt, 

 

Thank's for your answer, i have solved the problem with a "PLL" Block.
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