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ALTLVDS IP: Can serdes channels be placed into different IO banks?

Altera_Forum
Honored Contributor II
1,467 Views

Hello! 

 

I'm using cycloneV and trying to place ALTLVDS IP channels into different banks. Both TX and RX IPs are used with external PLL and channels placed into a single bank works fine, but if i place one channel into different bank then fitter error 175020 occurs. I've also tried using multiple IP instances, one for each bank, but still got the error :confused:. Kindly suggest a work around. 

 

Maybe answering this question will help alot, what are the requirements for fitter for LVDS IPs?
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6 Replies
Altera_Forum
Honored Contributor II
136 Views

could write more about the error? Maybe share the whole message?

Altera_Forum
Honored Contributor II
136 Views

I am using CycloneV SEBA4 device and implementing a design with ALTLVDS_TX and RX IPs with 5 channels. I am using IOBanks 4A,3B and 5A with PLL of bank 4A with IP internal PLL settings. All channels are identical and "analysis & synthesis" is successful, but fitter generates error 175020 for one TX channel, which is placed in bank 3B(DIFFIO_TX pin). I have compiled the design on quartus 15.0 and 15.1 both, and received the same error. 

 

I have used this solution :- https://www.altera.com/support/support-resources/knowledge-base/solutions/fb78288.html 

I get the critical warning of PLL not being in LVDS mode, as suggested in the solution. But still fitter generates error. Kindly suggest a probable cause and workaround for this error. 

Complete error is shown below 

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)).  

Error (175020): The Fitter cannot place logic pin in region (9, 0) to (22, 0), to which it is constrained, because there are no valid locations in the region for logic of this type. 

Info (14596): Information about the failing component(s): 

Info (175028): The pin name(s): lvds_tx_master_0_lvds_out_lvds_tx[3] 

Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: 

Info (175015): The I/O pad lvds_tx_master_0_lvds_out_lvds_tx[3] is constrained to the location PIN_AE7 due to: User Location Constraints (PIN_AE7) 

Info (14709): The constrained I/O pad is contained within this pin 

Error (175010): Location failed detailed legality checks (1 location affected) 

Info (175029): pin containing PIN_AE7
Altera_Forum
Honored Contributor II
136 Views

it seems that the LVDS-Core is not able to route the Clock to all the high-speed-PINs. Try a free-run of the fitter (with no constraints for the Clock-PINs) to see what happens. Maybe you would need to use two different Clocks for the PLLs...

Altera_Forum
Honored Contributor II
136 Views

I am using only one external PLL. With this, I have successfully compiled the design with placing IOs in Bank 3,4 and 5, one bank each time. It works great but if i use two banks together, design fails.  

 

I have ran the fitter without any clock assignments like you suggested and still got the error.(Fitter has I/O placement optimization ON) 

 

UPDATE: 

I have tried with my clock constraints but no LVDS I/O constraints. Fitter compilation is successful with I/Os placed in bank 3,4, and 5. Unfortunately if I change the pins according to my development board , It fails.
Altera_Forum
Honored Contributor II
136 Views

so you see the problem. 

There are no paths between clock and data pins which met the requirements you gave it with constraining the pin-locations. 

It's really hard to get your problem correct. If you would post some more detail about it (maybe a block-diagram or some code with PIN-Assignments)?!
Altera_Forum
Honored Contributor II
136 Views
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