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Altera_Forum
Honored Contributor I
1,274 Views

ALTLVDS_RX megafunction

Hi, guys: 

 

when i build a new project with HDL and megafunction , I use the ALTLVDS_RX for adc data(8 channels and deserialization factor is 1) and it works . Now, I want to generate a system in Qsys(adc + Nios ii + DDR2), how can i get the adc data ?  

 

The adc is 400 Msps. 

 

Any help may be appreciate. :o
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10 Replies
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

Hi, guys: 

 

when i build a new project with HDL and megafunction , I use the ALTLVDS_RX for adc data(8 channels and deserialization factor is 1) and it works . Now, I want to generate a system in Qsys(adc + Nios ii + DDR2), how can i get the adc data ?  

 

The adc is 400 Msps. 

 

Any help may be appreciate. :o 

--- Quote End ---  

 

 

You have to create an Avalon-ST streaming 'source' component for the ADC. 

 

You then need to create an Avalon-ST 'sink' to on-chip RAM, or some sort of fast memory device. Because you do not have an infinite amount of RAM, that sink component will need some form of capture enable controller - when enabled it generates addresses to RAM. 

 

If you use dual-ported RAM, then you can access the ADC captured data from the RAM via an Avalon-MM slave on the other port. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

You have to create an Avalon-ST streaming 'source' component for the ADC. 

 

You then need to create an Avalon-ST 'sink' to on-chip RAM, or some sort of fast memory device. Because you do not have an infinite amount of RAM, that sink component will need some form of capture enable controller - when enabled it generates addresses to RAM. 

 

If you use dual-ported RAM, then you can access the ADC captured data from the RAM via an Avalon-MM slave on the other port. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Hi, dwh@ovro.caltech.edu (http://www.alteraforum.com/forum/member.php?u=21847) : 

 

Thanks !  

 

And what are Avalon-ST 'source' and 'sink' ? How about SG-DMA ? 

 

On my board, a ddr2 is used for Nios ii CPU ,and I allocate some space for adc data . So I want to stream the adc data into ddr2 sdram and then stream out via uart port. 

 

Which Avalon-ST components are all right ?
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

 

And what are Avalon-ST 'source' and 'sink' ? 

 

--- Quote End ---  

 

 

Altera's definition of a streaming bus. Read the Avalon Interface Specification. 

 

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

 

 

--- Quote Start ---  

 

How about SG-DMA ? 

 

--- Quote End ---  

 

 

You still need to make the ADC look like an Avalon-ST component, so that you can connect it to a DMA controller. 

 

 

--- Quote Start ---  

 

On my board, a ddr2 is used for Nios ii CPU ,and I allocate some space for adc data . So I want to stream the adc data into ddr2 sdram and then stream out via uart port. 

 

Which Avalon-ST components are all right ? 

--- Quote End ---  

 

 

There are DMA controllers that can transfer data between an Avalon-ST component and bus master an Avalon-MM bus to access a DDR controller. I've never used any of them. I just write my own when I need them. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
106 Views

Thank you very much ! 

 

So, you mean that an Avalon-ST component and a SG-DMA will be ok, and I don't need a altlvds_rx block(.bsf) in my top-level .bdf file. Is it all right ?
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

 

So, you mean that an Avalon-ST component and a SG-DMA will be ok, and I don't need a altlvds_rx block(.bsf) in my top-level .bdf file. Is it all right? 

--- Quote End ---  

 

 

How do you interface to your ADC at the moment? Are you interfacing using LVDS pin constraints and then using DDR registers with a 200MHz clock, or are you using a SERDES (altlvds_rx) component? Either way, you can create an Avalon-ST component that includes that logic. You really need to start moving away from .bsf and learn a hardware description language. It'll make this sort of design significantly easier. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

How do you interface to your ADC at the moment? Are you interfacing using LVDS pin constraints and then using DDR registers with a 200MHz clock, or are you using a SERDES (altlvds_rx) component? Either way, you can create an Avalon-ST component that includes that logic. You really need to start moving away from .bsf and learn a hardware description language. It'll make this sort of design significantly easier. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

With another project I interface to ADC with the altlvds_rx . The ADC data is buffered in on-chip memory. It works. 

 

Just now, I want to store the ADC data on ddr2 sdram. But I don't know how to control the ddr2 with Verilog-HDL and the ddr2 controller in megafunction. So I am trying to implement that with Nios II.  

 

Luckily, my program can run on the ddr2 now. And then, I need your help that how to stream the ADC data into the ddr2(I allocate some space on the ddr2 for ADC data). 

 

The ddr2 clk is 150Mhz, the adc data is 8-bits and the ddr2 data width is 16. 

 

How to resolve the ADC data ? Can the Nios II CPU deal with the 400Mbps ADC data ?
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

With another project I interface to ADC with the altlvds_rx . The ADC data is buffered in on-chip memory. It works. 

 

--- Quote End ---  

What was the clock-rate inside the FPGA? 200MHz or did you demultiplex it further? How did you write it to on-chip memory? 

 

I assume you had some form of address generator and wrote the data until the RAM was filled. 

 

Think about how you would change that design to turn it into a 'stream'. 

 

The 'stream' from the ADC is a fire hose, it can never be stopped. The RAM is like a bucket. It can only handle a certain amount of data before it is filled. So how do you fill the RAM without it over-flowing? You enable writes to it until it is filled, and then you ignore the ADC data. 

 

So your Avalon system will consist of; 

 

- An ADC that is an Avalon-ST source 

- An on-chip SRAM Avalon-ST sink to write the data 

- An Avalon-MM register interface for enabling writes to the SRAM (enabling the address generator, and FSM that allows writes to the SRAM). 

 

By using dual-ported RAM, you can write to one side of the on-chip SRAM at the ADC clock frequency and then read from the other side of the SRAM at the Avalon bus frequency. 

 

Lets assume you modify your existing design to get this to work, and then ... 

 

 

--- Quote Start ---  

 

Just now, I want to store the ADC data on ddr2 sdram. But I don't know how to control the ddr2 with Verilog-HDL and the ddr2 controller in megafunction. So I am trying to implement that with Nios II.  

 

--- Quote End ---  

You don't need the NIOS II processor at all, you can use the JTAG interface (JTAG-to-Avalon-MM master). This interface is used to enable the controller and then poll for done via the registers interface. It never looks at the ADC data (since it is streaming too fast). Once the ADC data is in on-chip RAM or DDR, this interface can read the data from there. 

 

You do need to get the DDR2 controller working. Test it. See how fast you can write data to it. Try using the DMA controllers that Altera provides, or try writing your own. Once you understand how the DDR controller works, you can ... 

 

Modify your ADC design to write to an Avalon-ST sink that is implemented using a FIFO instead of RAM. The ADC data is written to the FIFO at the ADC clock rate, and the data is read from the FIFO at the Avalon bus clock rate. The data gets from the FIFO to the DDR via an Avalon-MM master; either a DMA controller, or one you write that controls the Avalon-MM side of the FIFO. 

 

Ultimately it comes down to how comfortably you are with coding as to how you implement each of the components. 

 

Its a lot to take on if you have not done this before, so start simple. Get each of the pieces working first, eg. for the DDR2 controller, get it working in simulation and then in hardware. Capture SignalTapII traces from the hardware and compare it to the Modelsim simulation waveforms. If you are using a 'slow' master like the NIOS II processor or the JTAG master, the performance will be bad, so add a DMA controller to the design, and DMA from on-chip SRAM to DDR2. This will be your benchmark for determining whether the DDR can handle your ADC data rate. 

 

Have fun! 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
106 Views

The clock-rate is 400MHz ,generating by a PLL.  

 

I write the ADC data into a fixed depth FIFO , just several thourands of bytes.
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

The clock-rate is 400MHz ,generating by a PLL.  

 

I write the ADC data into a fixed depth FIFO , just several thourands of bytes. 

--- Quote End ---  

Did you perform a TimeQuest timing analysis to confirm that timing was met at this frequency? If timing was not met, you can demultiplex the data. But make sure you do a timing analysis. 

 

If you configure the altlvds_rx for 1:2 mode, then the PLL will generate a 400MHz clock for capturing data bits, and a 200MHz clock for capturing demultiplexed-by-2 data. This will use the DDR registers in the I/O elements. 

 

If you use higher demultiplexing factors, then the SERDES shift-register will be used. Read some details here for a 1GHz ADC: 

 

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf

 

Your new design can still use the FIFO, but once you start writing to it with the ADC, your Avalon-MM master would start reading from it, and then writing the data to the DDR controller. 

 

You first need to determine whether the data rate of the ADC can be matched by the DDR interface. For DDR its not just a simple matter of clock frequencies. You have to determine the average data rate over a large number of bursts that include lost clocks due to refresh and page accesses. Once you know that your DDR can keep up, you can work on creating an Avalon-MM master for the FIFO-to-DDR transfers. 

 

It might seem like the more complicated way to go, however, the DDR controller is best used with an Avalon-MM interface (since that might be your only choice). So, its best to live with what you have and start there. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
106 Views

Nice , thanks again. 

 

Now I will try to use the Avalon-ST interface following your advice. If I can get the right ADC data , regardless of how much the frequency is, and then I will instantiate the ddr2 controller IP in my design.
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