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Hi, guys:

when i build a new project with HDL and megafunction , I use the ALTLVDS_RX for adc data(8 channels and deserialization factor is 1) and it works . Now, I want to generate a system in Qsys(adc + Nios ii + DDR2), how can i get the adc data ? The adc is 400 Msps. Any help may be appreciate. :oLink Copied

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Thank you very much !

So, you mean that an Avalon-ST component and a SG-DMA will be ok, and I don't need a altlvds_rx block(.bsf) in my top-level .bdf file. Is it all right ?- Mark as New
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The clock-rate is 400MHz ,generating by a PLL.

I write the ADC data into a fixed depth FIFO , just several thourands of bytes.- Mark as New
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Nice , thanks again.

Now I will try to use the Avalon-ST interface following your advice. If I can get the right ADC data , regardless of how much the frequency is, and then I will instantiate the ddr2 controller IP in my design.Topic Options

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