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ALTLVDS_RX

UMall1
New Contributor I
359 Views

I am using an ALTLVS_RX module in a Cyclone III device. Intel in its datasheet advises against using this module an recommends using BUS LVDS IO standards and logic to implement the function.

 

Why is this so? What are the odds of successfully implementing a Deserializer using this module and correctly decoding signals?

 

I simulate my design and in the simulation, I see correct operation. When I download it in a chip, the de-serializer fails to find signals I am looking for. I have tried all available means to synchronize with the source (Bit slip and all). However I do not see a signal.

 

When I open the Mega function to implement this design I program it to operate with a 360MHz clock with a 720Mbps signal. The Cyclone III datasheet clearly says that the maximum clock rate of this device is 350MHz. How is it then able to implement a 720Mbps systems using this interface? 

 

If the design is implemented with logic - what are the odds of meeting timing in such an endeavour. I assume a mega-function has special resources available to it that allow it to synthesize high speed logic that exceeds the maximum operating speed of the device?

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5 Replies
EngWei_O_Intel
Employee
333 Views

Hi

 

Can you help me with following?

 

1. Which part of the datasheet doc you are referring to when you mentioned it is not recommended to use ALTLVDS IP? We can help to check if our interpretation is aligned.

2. When you mentioned that the de-serializer fails to find signals, do you mean the inputs are not toggling or the output is incorrect?

 

The data rate is limited by the IO specification per device family which we need to adhere to. By using the IP, you will be able to directly utilizing multiple capabilities that come together with it, which you will need to build it with manual logic coding.

 

Thanks.

UMall1
New Contributor I
323 Views

In the document found here:

 

LVDS SERDES Transmitter / Receiver IP Cores User Guide (intel.com)

 

On Page 4 you find the following note:

 

Note: Intel recommends implementing the Bus LVDS (BLVDS) I/O with user logic, instead of the ALTLVDS_TX and ALTLVDS_RX IP cores.

 

2. The output is incorrect.

 

EngWei_O_Intel
Employee
302 Views

Hi



There are benefits over multipoint application for using BLVDS:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51008.pdf#...


I crossed check the "High-Speed Differential Interfaces" section in

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51001.pdf


and Table 1–31 in

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf


The max data rate shall be 740 Mbps with freq of 370MHz if you are using Cyclone III LS device C7, I7 grade depending on the mode.


Thanks.




UMall1
New Contributor I
290 Views

That was very helpful. Thank you. I seem to be well within all the metrics. Can you give me a sample SDC file that shows all the parameters that an ALTLVDS_RX module expects in compile time.

UMall1
New Contributor I
228 Views

Continuing with our discussion - I am using a EP3C80F484C6N device that can support a high speed ALTLVDS_RX module.  In Figure 31

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf

It is noted that the device can support an interface with the following characteristics.

 

fHSCLK (input        Factor    Min        Max
clock frequency)   ×10         5            437.5MHz

 

Yet, when I synthesize my design, I receive the following critical warning. How do I handle this warning? I see correct behavior in hardware. 

 

Critical Warning (176575): Cannot implement PLL "DESERIALIZER_CAM:U_SENSOR_1|altlvds_rx:ALTLVDS_RX_component|DESERIALIZER_STEREOCAM_lvds_rx:auto_generated|lvds_rx_pll", because the input clock of the PLL "I_CLK_1" uses I/O standard 2.5 V and has a frequency of 360 MHz. However, the device only supports a frequency up to 250 MHz.


Critical Warning (176575): Cannot implement PLL "DESERIALIZER_CAM:U_SENSOR_0|altlvds_rx:ALTLVDS_RX_component|DESERIALIZER_STEREOCAM_lvds_rx:auto_generated|lvds_rx_pll", because the input clock of the PLL "I_CLK_0" uses I/O standard 2.5 V and has a frequency of 360 MHz. However, the device only supports a frequency up to 250 MHz.

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