Hi,I am working with Cyclone IV E EP4CE22F17C6 and the ALTLVDS megafunction. One bit that puzzles me is the achievable data rate. According to the datasheet, when I use the LVDS megafunction in normal mode (i.e. not with the external PLL option) with true LVDS transmitters embedded in the FPGA, I can specify maximum data rate of 840Mbps. If I am thinking right this equates to 840MHz bit clock. So here is my issue: How come I can specify that kind of data rate for the output, when the PLL in CIVE can generate maximum frequency of 472.5MHz. I know I am only supplying the slower clock to the ALTLVDS block, but how is the faster clock generated? It must come from somewhere. I would appreciate any clarification on the matter. Kris
LVDS signals are send and received by DDR registers, using a clock of half bit rate. Thus 840MBPS can work with available Cyclone clock speed. You should consider however, that the window for correct data receiption is rather small at 840 MHz. Unlike Stratix and Arria family devices, Cyclone has no means to adjust the receive clock to compensate for data skew. So you should check thoroughly, if 840 MBPS will work reliably for your application. Choosing a slightly lower bit rate will things much easier, if possible.