I am trying to create a signal integrity memory test between a Stratix IV and DDR3 DIMM. I want to specify the 72bits that are simultaneous on the bus and do that for all 8 bits of the burst. How does the 576bits of the logical data for ALTMEMPHY map to the 72bits of physical data? Thanks.
I believe its LSB to MSB. Use the example top project provided with the IP and a simulation to confirm.I recommend using UniPHY not AltMemPHY as this is the latest IP.