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ALTMEMPHY Logical Data Order

Altera_Forum
Honored Contributor II
‎12-16-2010 09:17 PM
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I am trying to create a signal integrity memory test between a Stratix IV and DDR3 DIMM. I want to specify the 72bits that are simultaneous on the bus and do that for all 8 bits of the burst. How does the 576bits of the logical data for ALTMEMPHY map to the 72bits of physical data? Thanks.

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Altera_Forum
Honored Contributor II
‎12-22-2010 09:49 PM
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I believe its LSB to MSB. Use the example top project provided with the IP and a simulation to confirm. 

 

I recommend using UniPHY not AltMemPHY as this is the latest IP.
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Altera_Forum
Honored Contributor II
‎12-27-2010 06:53 PM
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Thanks for that info. Unfortunately, I don't get to pick which PHY is used.

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