ALTMEMPHY port replication/DDIO_OUT WYSIWYG invalid splitter fan out

[Altera_Forum]

I am using the ALTMEMPHY in an Arria II GX. Just instantiated from MegaFunction Wizard. Everything compiles fine. 

 The issues come when I want to create multiple versions of an ALTMEMPHY/DDR2 signal.  I want to have one ALTMEMPHY controller for 6 DDR2 chips. I can specify the DQ width, the# of clk pins, and chip selects to get multiple copies of pins (except bank address and address pins). In this case my bank address is 3 bits and address is 14 bits.  Let's assume that I NEED to have 2 copies of the bank address, I try to replicate the bank address output of the ALTMEMPHY, and I get the following error: Error (15887): Output port "DATAOUT" of DDIO_OUT WYSIWYG "ddr2_sodimm:ddr2_sodimm_inst|ddr2_sodimm_controller_phy:ddr2_sodimm_controller_phy_inst|ddr2_sodimm_phy:ddr2_sodimm_phy_inst|ddr2_sodimm_phy_alt_mem_phy:ddr2_sodimm_phy_alt_mem_phy_inst|ddr2_sodimm_phy_alt_mem_phy_addr_cmd:half_rate_adc_gen.adc|ddr2_sodimm_phy_alt_mem_phy_ac:ba[0].ba_struct|altddio_out:half_rate.addr_pin|ddio_out_pgd:auto_generated|ddio_outa[0]" has invalid signal-splitter fan-outs.  I have tried an assign statement and a procedural assignment, but I get the same error with both.   My questions 1)Does ALTMEMPHY have a setting to specify the number of sets of bank address/address? 2)Is there a way to replicate the bank address? If not, why can't I replicate the bank address? I assume it is a timing thing?  A related but separate question 3)If I cannot replicate the bank address (or other sensitive DDR2 associated signals like ras/cas), but I am driving them to 6 different DDR2 chips, what is a good approach to make sure that I don't have a slow slew rate/timing issues?  -a)It seems like I could have separate ALTMEMPHY instances, but that seems to make things overly complicated.  -b)doing a good job making sure that the routes are short and I do fly-by routing as shown in the External Memory Interfaces Guide, Chapter 4? -c)something else?  4)Also, if I can't replicate RAS/CAS/WE/CKE, it seems like I can set the# of Chip Selects in the ALTMEMPHY Megawizard. But I have 6 DDR Chip selects, so I would I just choose 8 in the ALTMEMPHY Megawizard and only use 6 (as indicated in table 8 -12 in the external memory interface guide)? Would I have to worry about ALTMEMPHY writing to non existant DDR Chips# 7 and# 8 since I only have 6?  Thank you

[Altera_Forum]

you can replicate any control pin (no data) , but to do so you need to edit the top level ddr file and manually instantiate the additional alt_ddio blocks. these blocks are what limit just replicating the output signal as they instantiate blocks in the IOE. 

 --dalon

[Altera_Forum]

Thank you for your input. I think I understand what you are saying, it is the specifics of actually doing it that I'm not sure about. I guess I will try to dig through hierarchy to see how to try this.

[Altera_Forum]

Well, I didn't quite understand what you meant by: 

"edit the top level ddr file and manually instantiate the additional alt_ddio blocks"  Mainly I didn't understand it since I didn't think it would work. It seems this method wouldn't work because the additional instantiation of the alt_ddio at the top-level wouldn't have the inputs needed to replicate the original instance.  If I assumed that you meant bottom level instead of top level ddr file, I altered ddr2_sodimm_phy_alt_mem.v, and the ports connecting to the top level. In this style, I added generate statements to instantiate multiple ddr2_sodimm_phy_alt_mem_phy_ac to replicate the outputs. Actually full disclosure, I did it for the mem_we_n first since it seemed simpler than for the change for the mem_ba (bank address) that I originally asked about. But, I now see that the change for mem_ba should be about the same, specifically, generate multiple instances and add a new output to each module in the hierarchy for each instance, instead of changing the bus width as I did for mem_we_n.  Thank you

[Altera_Forum]

I actually just did this today. Mrjpharris, you are correct, they are not at the top level They are buried many levels in. I found them at the ddr3_controller_phy_alt_mem_phy.v level. And yes I went through all the brutal work of bringing out the signals for the other RAMs in the RANK. What I did was start with mem_we_n signal found his driver, and duplicated the instance, renamed it, and brought the output signal (of new name) out all the way through the top to hook up at device pins. Example: 

 Original WE driver:  ddr3_controller_phy_alt_mem_phy_ac# (  .POWER_UP_HIGH (1),  .DWIDTH_RATIO (DWIDTH_RATIO) ) we_n_struct (  .clk_2x (ac_clk_2x),  .reset_2x_n (1'b1),  .phy_clk_1x (phy_clk_1x),  .ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),  .ctl_negedge_en (ctl_negedge_en),  .ctl_add_intermediate_regs (ctl_add_intermediate_regs),  .period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),  .seq_ac_sel (seq_ac_sel),  .ctl_ac_h (ctl_mem_we_n_h),  .ctl_ac_l (ctl_mem_we_n_l),  .seq_ac_h (seq_we_n_h),  .seq_ac_l (seq_we_n_l),  .mem_ac (mem_we_n) );  So I duplicated the whole block, adding the extra WE to the new DDR3 chip in the RANK:  ddr3_controller_phy_alt_mem_phy_ac# (  .POWER_UP_HIGH (1),  .DWIDTH_RATIO (DWIDTH_RATIO) ) we2_n_struct (  .clk_2x (ac_clk_2x),  .reset_2x_n (1'b1),  .phy_clk_1x (phy_clk_1x),  .ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),  .ctl_negedge_en (ctl_negedge_en),  .ctl_add_intermediate_regs (ctl_add_intermediate_regs),  .period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),  .seq_ac_sel (seq_ac_sel),  .ctl_ac_h (ctl_mem_we_n_h),  .ctl_ac_l (ctl_mem_we_n_l),  .seq_ac_h (seq_we_n_h),  .seq_ac_l (seq_we_n_l),  .mem_ac (mem2_we_n) );  You have to do this with the ADDR, CAS, RAS, CKE, BA, CS_N, ODT and Reset. Its painful - but do just one, see if your error goes away for that one in particular, then the rest are easier, because you can follow the first signal you put in through each module and the others are located nearby, just make the new, extra versions.   Hope this helps anyone. What I found when trying to do this was the Data, DQS, DQ, DQSN pins all had to have their own paths, you cannot duplicate them (and this should make sense, as well). For example, I have two 16 bit DDR3 chips in my rank. The lower chip gets data(0:15) and thus DQs(0:1), DQSN(0:1), while the upper Chip gets DQ(16:31) and DQS(2:3) and DQSN(2:3)

[Altera_Forum]

Hi! 

 Also I have the same error if I try to split the address and control signals. (I am using a ddr2 with a CycloneIII) Is there a way to duplicate them without touch the controller files?  thanks