FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

ALTPLL LOCK Generation

Altera_Forum
Honored Contributor II
‎07-21-2009 08:50 AM
981 Views

Hello everyone, 

 

I am new to Quartus Tool. In one of my application I am using ALTPLL Megacore for generating High frequencys. To test my design I have two sets of testcases.  

1. Tx testcases 

2. Rx testcases 

In simulation, If I select all testcases for TX, it is running fine. Similarly for RX testcases.  

 

But If I select one each from both the test sets, my PLL is not locking again for second testcase even though the first testcase was successfully completed. clock is still there at the input of the PLL. 

 

Remember, In each testcase, I am resetting and Initializing the DUT and providing the required information. 

 

Thanks & Regards
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.