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ALTPLL Output Error


I am porting a number of legacy systems created for a Cyclone II chip to a MAX10 ( 10M50DAF484C6GES) using Quartus Prime v17.1. The legacy systems have a variety of clocks that were originally created using counters and as much as possible I want to migrate the clock generation into PLLs.  Some of the required clock frequencies are so low that the IP Wizard tells me that they cannot be implemented in the PLL and I understand that.  For one frequency however, 10KHz, the wizard says it is valid and that the PLL can be configured to produce it but in simulation the output is not working.  I am using a 50MHz input clock for the PLL ... all higher frequencies simulate fine.  Am I doing something wrong or is the Wizard wrong when it tells me that it can create the 10KHz clock? Thanks.

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The PLLs are not really designed to get such a low frequency

As per datasheet of cyclone II & Max 10 we can't generate frequency of 10 Khz.


Yes, you can configure the pll for low frequency without any error but actual frequency implemented is different, even lock will be not be asserted practically.

Can check the same from altera PLL IP try by giving output clock of 10Khz you may see actual frequency in text box is different.(alt_pll is same as altera_pll)


You can write a simple clock divider and generate required frequency.


Let me know if this has helped resolve the issue you are facing or if you need any further assistance.


Best Regards,

Anand Raj Shankar


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