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Altera_Forum
Honored Contributor I
903 Views

AN690 (S5 PCIe reference design) Testbench Support

Hello, 

I apologize if this has been asked and answered already, but I'm having trouble generating BFMs for this reference design: 

http://www.altera.com/support/refdesigns/ip/interface/ref-pciexpress-avalonmm-hp.html 

I am able to step through AN690 and obtain the output from the provided Linux drivers, but am a bit wary about working with this without simulation. I attempted to regenerate the system in Qsys with these settings: 

Create simulation model: Verilog 

Create testbench Qsys system: Standard, BFMs for standard Qsys interconnect 

Create testbench simulation model: Verilog 

The regeneration of the system threw a few errors, though. The attached screenshots show them as well as the partially condensed Qsys schematic. Are testbenches provided for this design? 

Thanks, 

Neophyte
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2 Replies
Altera_Forum
Honored Contributor I
22 Views

I'm revisiting this problem that I have had with the Modelsim-Altera simulation of this reference design. The errors caused from generating the BFMs were caused by the inclusion of the SV HIP Status Output Bridge. Removing this device from the design allows for their generation in Quartus 13.1, but problems still remain. Sourcing msim_setup.tcl in Modelsim-Altera, then entering 'ld_debug' and finally 'run -a' causes the simulation to start and eventually error out. The logs show three irregularities: 

# ERROR: The attributes for bit 'rdynamic_sw' have illegal conflicting values 

# ERROR: Txelecidle not asserted in P1 state 

# FATAL: 97272 ns Current Link Speed is Unsupported # FAILURE: Simulation stopped due to Fatal error!# Break in Function ebfm_log_stop_sim at ./..//top_tb/simulation/submodules//altpcietb_g3bfm_log.v line 118 

 

Did I miss a step in properly generating the simulation files? I'm not sure where to proceed from here. 

 

Thanks, 

Neophyte 

 

# module stratixv_hssi_pma_rx_deser : simulation model silicon_rev = "reve"# module stratixv_hssi_pma_cdr_refclk_select_mux : simulation model silicon_rev = "reve"# module stratixv_hssi_pma_tx_cgb : simulation model silicon_rev = "reve"# ERROR: The attributes for bit 'rdynamic_sw' have illegal conflicting values .. # 495000: INFO: top_tb.top_inst_reset_bfm.reset_deassert: Reset deasserted# INFO: 560 ns Completed initial configuration of Root Port. # INFO: 3729 ns EP LTSSM State: DETECT.ACTIVE # INFO: 3829 ns RP LTSSM State: DETECT.ACTIVE # INFO: 3889 ns EP LTSSM State: POLLING.ACTIVE # INFO: 3989 ns RP LTSSM State: POLLING.ACTIVE # INFO: 6549 ns RP LTSSM State: POLLING.CONFIG # INFO: 16753 ns EP LTSSM State: POLLING.CONFIG # INFO: 17969 ns EP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 18325 ns RP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 19345 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 20277 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 20981 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 21905 ns EP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 22225 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 22453 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 23157 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 23477 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 24213 ns RP LTSSM State: CONFIG.COMPLETE # INFO: 24817 ns EP LTSSM State: CONFIG.COMPLETE # INFO: 26389 ns RP LTSSM State: CONFIG.IDLE # INFO: 37681 ns EP LTSSM State: DETECT.QUIET # INFO: 39285 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 40961 ns EP LTSSM State: DETECT.ACTIVE # INFO: 41057 ns EP LTSSM State: POLLING.ACTIVE # INFO: 52149 ns RP LTSSM State: DETECT.QUIET # ERROR: Txelecidle not asserted in P1 state# INFO: 53921 ns EP LTSSM State: POLLING.COMPLIANCE # INFO: 55845 ns RP LTSSM State: DETECT.ACTIVE # INFO: 56005 ns RP LTSSM State: POLLING.ACTIVE # INFO: 56497 ns EP LTSSM State: POLLING.ACTIVE # INFO: 59077 ns RP LTSSM State: POLLING.CONFIG # INFO: 69409 ns EP LTSSM State: POLLING.CONFIG # INFO: 70625 ns EP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 70981 ns RP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 72001 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 72933 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 73637 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 74561 ns EP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 74881 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 75109 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 75813 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 76165 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 76805 ns RP LTSSM State: CONFIG.COMPLETE # INFO: 77409 ns EP LTSSM State: CONFIG.COMPLETE # INFO: 81537 ns EP LTSSM State: CONFIG.IDLE # INFO: 81893 ns RP LTSSM State: CONFIG.IDLE # INFO: 82085 ns RP LTSSM State: L0 # INFO: 82344 ns # INFO: 82344 ns Configuring Bus 000, Device 000, Function 00 # INFO: 82344 ns RP Read Only Configuration Registers: ... # INFO: 82369 ns EP LTSSM State: L0 ... # INFO: 84069 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 96965 ns RP LTSSM State: DETECT.QUIET # ERROR: Txelecidle not asserted in P1 state# FATAL: 97272 ns Current Link Speed is Unsupported # FAILURE: Simulation stopped due to Fatal error!# FAILURE: Simulation stopped due to error!# Break in Function ebfm_log_stop_sim at ./..//top_tb/simulation/submodules//altpcietb_g3bfm_log.v line 118
Altera_Forum
Honored Contributor I
22 Views

The SV HIP Status Output Bridge doesn't has a simulation model, it is neccessary to disable this component in Qsys before generate the testbench.

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