FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5742 Discussions

AN829 - PCIe BAR[2] to read/write FPGA-EMIF-DDR4 over 1GB area

JET60200
New Contributor I
297 Views

hello ,

[ Scenario]  We can run AN829 PCIE driver on Arria10 EVM Board. 

In the FPGA design example, [pcie_a10_hip] -> [rxm_bar2]  can read/write to [ FPGA Emif -> ctrl_amm Slave Node] where we have 2GB DDR4 on fpga side (0x0 ~ 0x40000000). 

Linux Host can acess (read & write) the FPGA DDR4 through  PCIE_BAR2,  as following :

iowrite32 (cpu_to_le32(data), (u32 *)(bk_ptr->bar[BAR2]+byte_offset));

 

JET60200_0-1609813380641.png

 

My question:  on my test, that  PCIE_BAR2 can only maps "512MBytes" totally address space, which is mapped to FPGA-DDR4 "from 0x0 to 0x10000000" (the top 512MB).  If I need access to the FPGA-DDR4 1GB starting address 0x20000000 ~ 0x30000000, how can I realize this ?  Where to configure PCIE parameter to make BAR2 maps to this [0x2000 0000 ~ 0x3000 0000] ddr memory space ?  any ideas ?  

 

Thanks in advance    

 

 

0 Kudos
1 Solution
Deshi_Intel
Moderator
278 Views

I forgot to explain further. In AN829, DDR4 is connected to PCIe DMA port which means DDR4 can only be accessed via DMA control only.


That's why I suggested you to switch to use PCIe IP without enabling the DMA logic insides the IP. Then user can connect PCIe IP directly to memory (like DDR4) and access it.


Thanks.


Regards,

dlim


View solution in original post

6 Replies
Deshi_Intel
Moderator
284 Views

HI,


Platform designer only specify offset address, EMIF IP, on chip memory and PCIe IP setting.


Moving data between CPU host memory to FPGA DDR4 memory or on chip memory is controlled by DMA descriptor controller.

  • Meaning DMA driver software is the one responsible to configure DMA descriptor to tell it to access which memory address location.


I am not familiar with driver software design but you can try hack DMA driver design DDR4 address offset parameter to see if it helps to change the DMA memory access address to none default 0 address

  • Look for altera_dma.h in "AN829_driver" folder
  • goto either Arria 10 or Cyclone 10 section (depend on which FPGA product you are using), search for OFFCHIP_MEM_BASE parameter and change it to some other offset value
  • Just make sure the new offset value doesn't overwrite with on chip memory address space (ONCHIP_MEM_BASE)


If it still failed, then you will need to study on how to write up DMA driver...


Thanks.


Regards,

dlim


JET60200
New Contributor I
280 Views
Thanks Deshi for answer, We don't wanto engage in DMA operation, What we need is to change some FPGA IP setting to make the PCIE_BAR[2] base address to map to FPGA DDR4 address@0x1000_0000, thus we can use ioread/iowrite to access this part of DDR . Is this possble ? Thanks again
Deshi_Intel
Moderator
278 Views

HI,


It doesn't work like that. You are looking at example design that use (PCIe + DMA) IP.


If you just want to use PCIe IP that interact with memory directly, then pls consider to check out below example design that use (PCIe) only, no DMA


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
279 Views

I forgot to explain further. In AN829, DDR4 is connected to PCIe DMA port which means DDR4 can only be accessed via DMA control only.


That's why I suggested you to switch to use PCIe IP without enabling the DMA logic insides the IP. Then user can connect PCIe IP directly to memory (like DDR4) and access it.


Thanks.


Regards,

dlim


View solution in original post

JET60200
New Contributor I
273 Views
thanks @deshi, understand it. Appreciate your explaination
Deshi_Intel
Moderator
260 Views

You are welcome !


Reply