API calls failed while running PCIe DMA transfer example design

[Sijith]

Hi,

I was working the PCIe DMA transfer example design for Arria 10. I have added a counter custom IP which counts upto 1000, and An Avalon FIFO IP with the design. My intention is to write the data created in counter to DDR4 and then use the DMA API call (provided by Terasic in Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4.cpp) to read them from PC.

Even if I follows the steps given in the User manual of DE5a_DDR4_NET (attaching the manual. The chapter-7 section 7.6 is what I was following), the DMA API calls to read data fails. I would like to know why I could not run Read DMA API from the PC.

The It would be great if someone could give any helping hand. I am attaching the error message (Crash_op.PNG). 

I am just listing the procedure I followed,

1. Installed both DDR4 2400 4GB SODIMM on the FPGA board. 

2. Connected the FPGA board with PC through PCIe. 

3. Configured FPGA with DE5A_NET.sof (here the design .sof having PCIe DMA transfer example design + Avalon FIFO + Counter custom IP) by executing the test.bat. 

4. Restart Windows 

4. I could see the PCIe driver in the device manager (Windows has detected the FPGA Board). 

7. Executed the PCIE_DDR4.exe. Then  in the menu putting the options 3, 4 and 5 gives the failure.

FYI: I have been using Quartus Prime Pro 18.1 in Windows 10. 

[treble99]

Hello Wincent,

   Thank you for the link. I went through it. I also found this link to be helpful:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Avalon-BFM-Test-Program/m-p/111682


I understand the following. Please correct me if I am wrong.

1. The BFMs need to be driven by another testbench program (different from setup tcl script). This would be a systemverilog .sv program.

2. My reference design has several BFM provisions I can just drive the one I want.

3. For the MUT instantiation, I found it under the generated tb file :  `ep_g3x8_avmm256_integrated_tb/ep_g3x8_avmm256_integrated_tb/sim` This is one level above the mentor directory.

I am now setting up my own test bench program and trying to get it to work.

I will get back to you with more precise questions based on how it works.

Thank you,
Manish

[Wincent_Altera]

Hi,

I wish to follow up with you about this IPS case.

Did you get the bench up ?

Regards,

Wincent_Intel

[treble99]

Hello Wincent,

I have a skeleton tb which I have based on the threads you mentioned. But it is still not complete. I am uploading a copy. (sim_tb.sv)

I have problem with inheriting the correct BFM, the ddr has several BFMs but which one would be correct? How to determine that?

Inheriting the BFM, what would be the path for it?

Can you confirm that the instantiation is correct?

I am also attaching the base .sv file that I am using as reference (sopc_system_bfm_master_tb.sv)

Let me know if you need more information.

Best,
Manish

[treble99]

Hello Wincent,

I realized I did not provide additional files. The project zip was exceeding the size. I am attaching a zip file (PCIE_DDR_ref_files.zip) which contains the generated tcl and testbench output(only some of it.)

Also attaching the source repo for re-creating the Design in case you would like to do that (PCIE_DDR.zip)

Let me know if you would require any more information.

Best,

Manish

[Wincent_Altera]

Hi,

Sorry I am a little bit lost.

Previously when I talking with Sijith, he mention that follow the PCIe_ddr4 design. the DMA APi call to read data is fails.

Also found that API call failure.

Then we move to simulation and check if the same behavior happen or not.

If this is emif simulation, you may refer to https://www.youtube.com/watch?v=iCr-0eOwo9o&ab_channel=IntelFPGA

And see if you are able to seeing something similar as the hardware or not.

Last I would like to confirm back with you, is this is a PCIe design or EMIf design ?

the error is happen in emif part of PCIe HIP part ?

Regards,

Wincent_Intel

[treble99]

Hello Wincent,

Then we move to simulation and check if the same behavior happen or not. And see if you are able to seeing something similar as the hardware or not.

This is still what we want to do. But we dont have all the parts for it. I am going to review the video and get back to you.

Last I would like to confirm back with you, is this is a PCIe design or EMIf design ?

the error is happen in emif part of PCIe HIP part ?

We are lost in this part to identify where this is happening. I have taken up Simulation efforts. This is Terasic's PCIe_DDR example. It has a PCIe Hard IP as well as DDR emif. Please see attached Image.

Best,
Manish

[Wincent_Altera]

Hi Sijith,

1. Did you able to capture the LTSSM signal from Signal tap ? just to ensure the PCIe is able to link up.
2. Did you connect the PCIe external power connector to 6-pin 12V DC power connector in the FPGA to avoid FPGA damage due to insufficient power ?

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[treble99]

Hello Wincent,

Please give me until Monday to try all your recommendations. Please do not close the ticket until then.

Manish

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[Sijith]

Hi Wincent,

Please do not close the ticket as we are still working on it.  Sorry for bit delay in response and now trying to catch up to the pace.

Did you able to capture the LTSSM signal from Signal tap ? just to ensure the PCIe is able to link up.

No we could not capture the LTSSM signal from Signal Tap at first place. Will retry it and update you ASAP.

Did you connect the PCIe external power connector to 6-pin 12V DC power connector in the FPGA to avoid FPGA damage due to insufficient power ?

Yup absolutely! we did connect the external power connector.  

The API call failure I mentioned before is that happened when Adzim provided some modified VHDL code for the PCIe_DMA transfer example design + Avalon FIFO + counter (basically he tested altered the signal connectivity). While programmed with that modified design, I got API call failure.

[Wincent_Altera]

Hi Sijith,

The API call failure I mentioned before is that happened when Adzim provided some modified VHDL code for the PCIe_DMA transfer example design + Avalon FIFO + counter (basically he tested altered the signal connectivity). While programmed with that modified design, I got API call failure.

>> Can you file another forum case and select the "catagory" as EMif so that Adzim can take loop back on the API failure ?

Regards,
Wincent_Intel

[Wincent_Altera]

Hi

A fews follow up had been make.

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

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Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel