ARRIA V GZ PCIe Equalization

[TomLithgow]

Hello,

We have a design based on the ARRIA V GZ utilising PCIe Gen3.

Some questions have been raised around the specific Equalization settings being applied under various conditions, but at the moment the PCIe config space will read back default/zero values for the Equalization settings.

It was noticed that there is a Knowledge Base Post for the ARRIA X device stating that some register read back will give incorrect values due to a silicon issue.

https://www.intel.com/content/www/us/en/support/programmable/articles/000077021.html?wapkw=ARRIA%20V%20PCIe%20Gen3%20EQ%20preset

First of the question is (possibly for @intel );

Does this issue also affect the ARRIA V GZ device?

If not;

Is it expected to be able to read back the Hinted/Applied Equalization settings of the device through the PCI config space? 
Any pointers woudl be appreciated.

Regards,

[wchiah]

Hi,

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best regards,

Wincent_Intel

[wchiah]

Hi,

As the knowledge based mentioned, it only applicable to Intel Arria 10 PCIe hard IP device.

Do you facing any error using Arria V ?

Regards,

Wincent_Intel

[TomLithgow]

Hello Wincent,

Thank you, we just wanted to verify that the same issue did not exist for the older ARRIA V GZ device.

We are working to confirm if the Equalization settings are correctly being applied to the PCIe link, when we read the PCI config space via the host we see values that seem to always be default:

11:8 - Upstream Port 8.0GT/s Transmitter Preset (HwInit)
This field holds the Transmit Preset value sent or received during 8.0GT/s Link Equalization.
- 0000b      =      De-emphasis = -6dB; Preshoot = 0dB

and

14:12 - Upstream Port 8.0GT/s Receiver Preset Hint (HwInit)
This field holds the Receiver Preset Hint value sent or received during 8.0GT/s Link Equalization.
- 000b      =      -6dB

 This has raised some concern as to whether the Equalization settings negotiated is in fact being applied.

Regards,

Tom 

[TomLithgow]

Hello Wincent,

Just to add to the above, a specific question;

• How can we know if Link training has occurred correctly i.e. that the PCIe Physical layer EQ in the transceivers has been set up correctly?

Is there a mechanism that we can use to query/confirm the Transiever set up in regard to PCIe and the EQ presets?

Any guidance in this would be greatly appreciated.

Tom Lithgow

[wchiah]

Hi,

I think the resolution is provided in another forum loop.

https://community.intel.com/t5/FPGA-Intellectual-Property/Arria-10-FPGA-PCIe-3-0-Endpoint-is-not-compatible-with-PCIe-4-0/m-p/1470574#M27352

Let me know if you still have any other question.

Regads,

Wei Chuan

[TomLithgow]

Hello Wei Chuan,

Thank you, but not this is not the same issue.

I am aware of the PCIe limitation regarding Data Link Feature Exchange.

What we are looking for in this support thread is a way to check the applied PCIe Equalization parameters, or Preset, after our PCIe add in card is enumerated and detected and working correctly.

What is the recomended processes to read the applied Equalization Settings on the PCIe transcievers within our Firmware project?

Regards,

Tom Lithgow

[wchiah]

Hi Tom,

To check the link equalization, you may refer to

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/phy-for-pcie-pipe-link-equalization.html

But it is for gen3 data rate for PIPE mode.

Hope this able to help you.

Regards,

Wincent_Intel

[TomLithgow]

Hello Wincent,

Thank you for the link, and this information.

I have reviewed this section before and it is quite infromative about the processes required and what is and isn't supported.

It does not really give very much detail about how this should/can be achieved.

I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.

Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?

E.g. it should not be on before Stage 2?

Also I noted the comment about the AEQ Registers, I believe that this is the detail that we have been looking for:

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/transceiver-reconfiguration-controller-81921.html

equalization results

This is the value set by the automatic AEQ adaptation performed at startup. If you choose to perform manual equalization using the linear equalizer, you can use this value as a reference. Although automatic and manual equalization do not provide identical functionality, specifying this value enables manual equalization to approximate the original setting.

Regards,

Tom Lithgow

[wchiah · Accepted solution]

Hi Tom,

I did note a comment about enablign AEQ during Phase 2, I think we have this enabled in Quartus project but not sure if this is only being enabled durign Phase 2. Will check this at our end.

Can you confirm that this needs to be enabled/disabled programatically, and only during stage 2?

E.g. it should not be on before Stage 2?

>>I never encounter this question before , but I just answer to you based on my own understanding, please correct me if you feel I am wrong. During the Equalization phase (Phase 2), the AEQ feature is used to adjust the equalization settings of the PCIe transceivers in real-time based on the quality of the received signal. This helps to ensure a stable and reliable data transfer link.

The AEQ feature can be enabled or disabled programmatically in your firmware project using the appropriate registers provided by the PHY IP Core. It is recommended to enable the AEQ feature only during Phase 2 of the PCIe link training process and disable it before Phase 2 to avoid any interference with the link training process.

Let me know if you have different thoughts.

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[TomLithgow]

Hello Wincent,

Yes, I think we have the answer that we had been looking for.

The EQ parameters and Controls are part of the Tranciever Reconfiguration Controller registers, not in the PCIe block, which makes sense. We can read the EQ  results as per the registers mentioned here;

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/transceiver-reconfiguration-controller-81921.html

Also noted that below it is stated that the transcievers can be manually read/written as explained here;

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/changing-transceiver-settings-using-01356.html

Thank you for the assistance.

Regards,

Tom Lithgow

[wchiah]

Hi

Glad that it answering your question.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel