ARRIA10 GX calibration issue - Manual says 2 things one versus other ... (?)

[APaci1]

Hello!

I have a high speed DAC and ADC with JESD interface.

Different jesd parameters due to components forced me to use two different GX interfaces (on half duplex mode..)

The problem is that on our HW, we have a clk125 for GX that is not present at power up (it is from programmable device connected to Nios processor and so it runs only after nios config)

So, intial calibration of fPLL and GXs fails (clock not present)

Manuals says that reconfiguring of FPLL and Transceiver is possible "hot recalibration" (to solve ref clock lack at power on), making IPs as reconfigurable via Avalon interface.

Well, if I set avalon interface on two different GXs components. Reconfig CANNOT BE DONE , due to Quartus compilation error 12289 :

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/ehssi_hssi_xcvr_reconfig_group_merge_fail_msg.htm

Manual report a workaround, it say to remove group of gx nets.

But, if we cut on the .qsf file the "group gx rows" , on the next compilation we encounter another error: the 12787.

The workaround that Intel suggests it to reinsert Group on Qsf.. (!!!)

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/ehssi_hssi_illegal_tx_rx_merge.htm

well, at this point Intel suggestions give us a "infinite loop"...

At this point, the solution is connect only one reconfiguration interface of rx section and fPLL, leaving other tx Gx not reconfigurable. (But so we don't make recalibration of tx pma gx.)

This should be the unique solution???

Or it exists another possibility (script or pin or other) to perform "warm" recalibration of these GX after power on? This is the only thing needed for us.

Thansk for any suggestion to Intel and Intel fellows and expert GX guys!

Good work to everyone from Center Italy!

[SreekumarR_G_Intel]

Thank you for the detalied explanation ;

Would it possible to share the design and i will start from there ; It will save a lot of time for both of us.

Thank you,

Regards,

Sree

[APaci1]

Hello Sree,

I managed to solve, the solution is explained in chapter 6.14 of the User Manual Intel arria 10 Transceiver PHY,

It says:

Figure 280. Independent Instances of Simplex TX/RX in the Same Physical Location

Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores

To merge reconfiguration interfaces across multiple IP blocks, you must follow these rules:

1. The control signals for the reconfiguration interfaces of the IP blocks must be driven by the same source. The reconfig_clk, reconfig_reset, reconfig_write, reconfig_read, reconfig_address, and reconfig_writedata ports of the two interfaces to be merged must be driven from the same source.

2. You must make a QSF assignment to manually specify which two reconfiguration interfaces are to be merged.

a. Use the XCVR_RECONFIG_GROUP assignment.

b. Set the To field of the assignment to either the reconfiguration interfaces of the instances to be merged or to the pin names. The reconfiguration interface has the string twentynm_hssi_avmm_if_inst.

c. Assign the two instances to be merged to the same reconfiguration group.

You cannot merge multiple reconfiguration interfaces when NPDME, optional reconfiguration logic, or embedded reconfiguration streamer are enabled in the Native PHY IP core. (63) You cannot merge the TX and RX channels when the Shared reconfiguration interface parameter is enabled in the Native PHY IP core Parameter Editor.

You can merge channels only if the reconfiguration interfaces are independent.

I applied this and now the compilation is ok and i can recalibrate the transceiver, just i can only write and not read the reconfiguration interface but it is ok the same.

Thanks

Best regards

[SreekumarR_G_Intel]

Thank you for the prompt response :)

Regards,

Sree