AVALON-MM Master Template on DE10 Lite

[Altera_Forum]

Hello, I am new to FPGA Development and in need of some help here. 

  I own a DE10 Lite and wish to build a system to read the contents of SDRAM. At first, all I want to do is read the contents of SDRAM. Later, I plan to update the RAM using the spi_slave_to_avalon_mm_master_bridge qsys component.   The problem I am facing in my code is that when data is read from memory, it appears to come back repeated. Let me explain,   I have an FPGA VHDL file/code that responds to a button press, the write process. When a button is pressed (called trigger), this process sequentially writes a counter to an incrementing memory addresses. The counter incrementally goes up with the address. The process stops at 19000. Memory address 0, should have a value of 1, memory address 2 should have a value of 2, etc.    Part of the system was setup in Platform Designer/Qsys. This part uses the SDRAM controlor, spi_slave_to_avalon_mm_master_bridge and the Avalon-MM Master Templates.    There is another process that also responsd to the trigger press, the read process. When the trigger is pressed, this process, sets up a delay of about 30000. So, when this process kicks off, all data should have already been written. This procesds, starts by looking at the contents of mem addrress 0 and issues a read, the read returns, memory address 1 is then read in then same way.   I note that this process reads values 1,1,2,2,3,3,4,4,5,5 when it should be reading values of 1,2,3,4,5 etc.   I'm pretty sure that the mem write porocess wrote sequentially in incrementing mem address correctly. I have beeen using signal tapp to see what is happening and suspect there is an error in the Avalon-MM Master Templates (Read), the write template is probably ok? not sure.   The SDRAM is 16 bits data. My process responds to the signals done, data_available, etc as I think it should with the proper timing, yet the data does not return properly. I am sure that the data is being written to the SDRAM correctly. If I change the write process to start at a number such as 30,    The read process reads 30,30 31,31 , 32 ,32 , etc   The problem seems to be somewhere in the read process. Please advise how I can alleviate this. This is my first, and rather deep foray into FPGA dev and I want tobe successfull at this task of reading memory.     I have attached the project. I suspect, after trying a lot of variations, that the Avalon MM read template just doesn't wrok as advertised. I am looking ayt the documentation dated 09/08/2008. Note this was some template downloaded from Alter and added to platform designer.   Can someone look at this project and offer suggestions as to what to do? I would like to use the spi_slave_to_avalon_mm_master_bridge component and rely on the system intercoinnect fabric to arbitrate the readers and writers of SDRAM. Thanks, Jeff

[Altera_Forum]

Are you incrementing the address only by 1 on each access? Contrary to the Avalon MM slave interface, the Avalon MM master interface always uses addresses in the 8-bit space. So for example if you are doing 16-bit data accesses, you need to increase the address by 2 for each access. 

On an Avalon bus with a 16-bit data, reading/writing at addresses 0 and 1 will have the same effect.

[Altera_Forum]

--- Quote Start ---  Are you incrementing the address only by 1 on each access? Contrary to the Avalon MM slave interface, the Avalon MM master interface always uses addresses in the 8-bit space. So for example if you are doing 16-bit data accesses, you need to increase the address by 2 for each access. On an Avalon bus with a 16-bit data, reading/writing at addresses 0 and 1 will have the same effect.  --- Quote End ---    Thank you,  I was incrementing the address by 1. When I changed it to increment by 2, it now looks like it properly works. I will do some more tests, but I think that was the issue.  Jeff